Session 12-2
An On-Chip Noise Canceller with High Voltage Supply
Lines for Nanosecond-Range Power Supply Noise
Abstract
| An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoup-ling capacitors and the power supply lines respectively. |