Session 7-3

A 7b 1.1GS/s Reconfigurable Time-Interleaved
ADC in 90nm CMOS

 

Abstract

A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four Sub-ADCs are modulated to the frequency of Fs/2 by the reference- and opamp-sharing techniques. Fabricated in 90nm CMOS, the 7bit ADC has an ENOB of 6.5 at 1.1GHz sampling rate. The I/Q ADCs totally consume power of 92mW from a 1.3V supply.