2004 VLSI Circuits Short Course Program "Designing High Data Rate Interfaces" Wednesday, June 16, 2004 Tapa III Organizers/Chairs: Ajith Amerasekera, Texas Instruments Masayuki Mizuno, NEC 8:30 a.m. Introduction Ajith Amerasekera, Texas Instruments 8:45 a.m. System Buses and Interface Standards Stefanos Sidiropolous, Aeluros 9:45 a.m. External Memory Interfaces Hiroaki Ikeda, Elpida 10:45 a.m. Break 11:00 a.m. Chip to Chip Communication Kohtorah Gotoh, Fujitsu 12:00 p.m. Lunch 1:00 p.m. High Speed Backplanes Jaeha Kim, Seoul 2:00 p.m. Testability and Reliability Dan Weinlader, Accelerant 3:00 p.m. Break 3:15 p.m. Design for Signal Integrity and Packaging Brian Young, Texas Instruments 4:15 p.m. Interface Speed and Voltage Scaling Roadmap Ken Yang, UCLA 5:15 p.m. Conclusion Masayuki Mizuno, NEC