Best Student Paper Award Committees


2013 SYMPOSIUM ON VLSI TECHNOLOGY

Welcome to the 2013 Symposium on VLSI Technology


Advance Program (as of June 6th)

We would like to cordially welcome you to the 2013 Symposium on VLSI Technology to be held from June 11-13 at the Rihga Royal Hotel in Kyoto, Japan. The VLSI Symposium has long been recognized as one of the premiere technical conferences introducing the latest technology advancements in semiconductor microelectronics, with no exception this year.

A unique aspect of this conference is, following a long tradition, that it is held jointly with The Symposium on VLSI Circuits. The co-location of these two Symposia provides the excellent opportunity to span the whole range from process technology to System-on-Chip integration, and to promote interactions between technologists and circuit/system designers in an open forum.

Research results presented at the Symposium on VLSI Technology comprise a broad spectrum of VLSI technology topics, including new concepts and breakthroughs in VLSI materials, processes, devices, interconnects, and packaging up to 3D-system integration. Beyond advanced theories, fundamentals, characterization, analysis, modeling, and reliability for VLSI devices, heterogeneous integration of non-Si materials/devices on large Si substrates and new functional devices beyond CMOS with a path for VLSI implementation will be discussed.

In recent years, when collaboration among transistor, circuits, and systems designers became critical to innovation, this conference enables attendees to gain a broad understanding of the latest advances that will drive the industry forward. This year, we have focused on many areas of joint interest between technology and circuits to create an outstanding technical program that will allow attendees to experience the unique value of this shared location.

To offer attendees an exquisite opportunity to learn about the latest advances in semiconductor devices and memory technologies and their implications for VLSI circuit design, we will start the symposium with a one day Short Course on “Technology Enablers for the Future Smart Society,” on June 10th. The lectures, given by industry and academic leaders in their respective fields, will address state-of-the-art topics that have a huge impact on our industry and are of interest to both Technology and Circuits attendees.

This year we have 15 regular sessions with 68 outstanding contributed papers and 8 invited papers. Two Technology Focus Sessions cover “3D System and Packaging” and “3D and Emerging Memory”. In addition, for the first time this year, two extended Joint Focus Sessions between Technology & Circuits on “Design Enablement” and “SRAM” will be held, where technology papers and circuit papers mixed in a whole afternoon session will encourage strong discussions and interaction between technologists on the respective subject

We invited two distinguished plenary speakers to present recent advances and new challenges related to VLSI technologies and applications. The Plenary Session on June 11th opens with “System Scaling and Collaborative Open Innovation,” presented by Jack Sun, Vice President of Research & Development and Chief Technology Officer, at TSMC and discusses new scaling paradigm by combining silicon wafer-based chip scaling with 3D chip stacking and industry-wide collaborative open innovation. The second talk entitled “System Design Considerations for Next Generation Wireless Mobile Devices” will be presented by Robert Gilmore, Vice President of Qualcomm. Dr. Gilmore will discuss the key challenges and potential solutions on silicon technology (e.g. power consumption, performance) and system architecture (e.g. PA, LNA, Filters) for mobile communication, associated with the explosive increase in demand for Smartphones with ever increasing capabilities, features and performance.

VLSI Technology Symposium evening Rump Sessions are well known for their selection of timely topics and enthusiastic discussions with technical leaders on the panel and in the audience. This year, we have again three Rump Sessions. The first one, “SOC vs. 3D IC in the More-than-Moore Era” is a joint session with the VLSI Circuits Symposium on the evening of June 11th. The remaining two sessions also held on the same day are “Low Voltage - How low can we go?” and “Novel hierarchy in Emerging Memory”.

We also have been organizing a luncheon talk for attendees of Circuits and Technology Symposia to enjoy informative and entertaining speeches on interesting topics in a relaxed atmosphere with excellent food. This year, it will feature the talk “Symbiosis with Lightning which is one of the most spectacular natural phenomenon” by Dr. Takeshi Kudo from Otowa Electric co., Ltd..

This year’s excellent technical program with an outstanding set of remarkable top quality paper has been compiled by the committee members, all world-wide leaders in the field of VLSI technologies. We are sure that you will enjoy the paper presentations, and we cordially invite you to participate in the lively discussions in and outside of the sessions and in an informal and convenient atmosphere.

This is a rich and exciting technical program, and we certainly hope that you will take advantage of the opportunities to network with your industrial and university colleagues between the technical sessions as well as have a productive and enjoyable experience.

We look forward to meeting with you at the Symposium in Kyoto.

Toshiro Hiramoto
Raj Jammy
Program Chair
Program Co-Chair


CONFERENCE SCHEDULE

Sunday,
6/9
8:00a-17:00p Registration
Monday,
6/10
7:30a-17:00p Registration
8:10a-17:15p Short Course (Shunju I)
Tuesday,
6/11
7:30a-17:00p Registration
8:30a-10:05a Session 1 T1: Welcome and Plenary Session (Shunju I, II)
10:30a-12:10p Session 2 T2: Highlight (Shunju I, II)
13:30p-15:35p Session 3 T3: Ge MOSFET (Shunju I)
Session 4 (Focus Session) T4: 3D System and Packaging (Shunju II)
15:50p-17:30p Session 5 T5: III-V MOSFET (Shunju I)
Session 6 (Focus Session) T6: 3D and Emerging Memory (Shunju II)
20:00p-22:00p Joint Rump Session (Suzaku I, II)
Technology Rump Session (Shunju I, II)
Wednesday,
6/12
7:30a-17:00p Registration
8:30a-9:50a C-Session 1 C1: Welcome Session (Shunju I, II)
C1: Executive Panel (Shunju I, II)
10:30a-12:35p Joint Focus Session (Circuits) C3(JFS): 3D Integrated Circuits & Applications (Suzaku I, II)
Session 7 T7: Advanced FinFET (Shunju I)
Session 8 T8: ReRAM 1 (Shunju II)
13:55p-16:00p Jumbo Joint Focus Session 1 JJFS1: Design Enablement (Shunju I)
Session 9 T9: PCRAM and MRAM (Shunju II)
16:10p-17:50p Jumbo Joint Focus Session 1 JJFS1: Design Enablement (Shunju I)
Session 10 T10: More than Moore (Suzaku I, II)
Session 11 T11: NAND and 3D NVM (Shunju II)
19:00p-21:00p Joint Banquet (Shunju I, II)
Thursday,
6/13
8:00a-17:00p Registration
8:30a-10:10a Session 12 T12: ReRAM 2 (Shunju II)
10:30a-12:35p Joint Focus Session (Circuits) C9(JFS): Emerging Memories (Shunju I)
Session 13 T13: RTN (Suzaku III)
Session 14 T14: Process Technology (Shunju II)
12:45p-14:05p Luncheon Talk (Suzaku II)
14:20p-16:00p Jumbo Joint Focus Session 2 JJFS2: SRAM (Shunju I)
Session 15 T15: Nanowire (Shunju II)
16:15p-18:20p Jumbo Joint Focus Session 2 JJFS2: SRAM (Shunju I)
Session 16 T16: Beyond CMOS (Shunju II)
16:15p-17:00p Session 17 T17: Late News (Suzaku II)




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