Committees Short Courses Call for papers Best Student Paper Award


2009 SYMPOSIUM ON VLSI TECHNOLOGY

Welcome to the 2009 Symposium on VLSI Technology

Welcome to the 2011 Symposium on VLSI Technology On behalf of the Organizing Committee, it is our great pleasure to invite you to the 2009 Symposium on VLSI Technology which will be held from June 15-17 in Kyoto, Japan. This symposium has been recognized as one of the premiere technical conferences on the latest research and developments in the field of VLSI technologies and their applications, and this year is no exception.

The Program Committee of this year has selected 82 top quality papers addressing a wide range of topics from 205 submitted papers, and has organized 22 technical sessions for the Kyoto symposium.
We are also delighted to have two very distinguished invited speakers for the plenary session. Dr. Ken-ichiro Mogi of Sony Computer Science Laboratories, Inc. will present a talk on “The Brain Science Collaborating with Semiconductor Technology (tentative)” and Dr. T. C. Chen of IBM T. J. Watson Research Center will give a talk on “Device Technology Innovation for Exascale Computing”.
Furthermore, this year we introduce three new sessions which consist of “Focus Session” to be held in the morning of June 15 and two “Special Sessions” to be held in the mornings of June 16 and 17. In the Focus session, 3D-System Integration technologies, which have become ever increasingly important for future technology generations, will be presented and discussed by 5 excellent invited speakers. They are Dr. S. Borkar of Intel, Dr. S.S. Iyer of IBM, Prof. M. Koyanagi of Tohoku University, Dr. S. Arkalgud of SEMATECH and Dr. W.-C. Lo of ITRI.

There are two topics covered in the Special Sessions: Explorative Research (ER) and Beyond CMOS (BC). “Explorative Research” deals with advances in physical analysis, materials science, and
modeling/simulation of VLSI. “Beyond CMOS” covers new functional devices beyond CMOS with a path for VLSI implementation and Theories and fundamentals related to such devices.
For the ER session, Prof. K. Shiraishi of Univ. of Tsukuba and Prof. S. Stemmer of UCSB are going to give invited talks. And Prof. H. Ohno of Tohoku University and Prof. J. Appenzeller of Purdue University are going to give invited talks for the BC session. Three regular papers are going to be presented for each session.
Three Rump Sessions are planned for the evening of June 15 as a means to facilitate informal discussion among attendees. Two of the Rump Sessions are regular sessions covering specific technology related topics of timely interest:
1. The Path Towards Sub 30nm Non Volatile Memories.
2. Key Technology Options for 16nm CMOS and Beyond.
3. A joint Session with the Symposium on VLSI Circuits focusing on the “3D-IC and Adv. Packaging”.
A one-day Short Course, scheduled for June 14 will cover “Outlook for 32/28/22nm Manufacturing”. This should be an excellent opportunity for experienced as well as new engineers to broaden their technical base.

The symposium registration fee covers all of the sessions including the Rump Sessions, the symposium proceedings, the symposium banquet, and a CD-ROM containing all of the contents of the Digests.
Registration for the Short Course includes the attendance to the short course as well as a booklet containing the short course presentation materials. The detailed registration fees and hotel reservation schedules are included in the Advance Program.
We look forward to seeing you at this very exciting symposium in beautiful Kyoto and we are sure that you will find the conference exciting and rewarding.



Masaaki Niwa

Ming-Ren Lin
Program Chair Program Co-Chair




CONFERENCE SCHEDULE

Saturday, June 13 8:00-17:00 Registration
Sunday, June 14 8:10-12:00 Short Course [Shunju I]
12:00-13:30 Lunch
13:30-17:15 Short Course [Shunju I]
Monday, June 15 8:30-10:05 Session 1 Welcome and Plenary Session [Shunju I, II]
10:40-12:20 Session 2A Strain Engineering [Shunju I]
Session 2B Resistance Memory [Shunju II]
12:20-13:40 Lunch
13:40-15:45 Session 3A Advanced Gate Stack [Shunju I]
Session 3B Random Telegraph Noise and Shot Noise [Shunju II]
16:00-18:05 Session 4A Focus Session-3D System Integration [Shunju I]
Session 4B Ge MOSFET [Shunju II]
20:00-22:00 Rump Sessions
Tuesday, June 16 8:30-10:10 Session 5A Nanowire FETs [Shunju I]
Session 5B Source / Drain Contact Technology [Shunju II]
10:30-12:35 Session 6A Variability I [Shunju I]
Session 6B Special Session-Beyond CMOS [Shunju II]
12:35-13:55 Lunch
13:55-15:35 Session 7 Highlights [Shunju I, II]
16:10-17:50 Session 8A Variability II [Shunju I]
Session 8B Advanced Source / Drain Engineering [Shunju II]
19:00-21:00 Joint Dinner
Wednesday, June 17 8:30-10:10 Session 9A Process Technology [Shunju I]
Session 9B Non-classical Transisters [Shunju II]
10:30-12:35 Session 10A NAND Flash Memory [Shunju I] -12:10
Session 10B Special Session-Explorative Research [Shunju II]
12:35-14:20 Lunch  
14:20-16:00 Session 11A CMOS Device Integration [Shunju I]
Session 11B Novel Memory [Shunju II]
16:15-17:55 Session 12A Floating Body DRAM and MRAM [Shunju I]
Session 12B High Mobility Devices [Shunju II]




PROGRAM

Monday, June 15

Session 1

Welcome and Plenary Session [Shunju I, II]
Chairpersons M. Niwa, Panasonic Corp.
M.-R. Lin, GLOBALFOUNDRIES

8:30

1-1
Welcome and Opening Remarks
   T. Mogami, Semiconductor Leading Edge Technologies, Inc.
C. Dennison, Ovonyx Technologies, Inc.

8:45

1-2
The Systematic Turn in Cognitive Neuroscience
Invited K. Mogi, Sony Computer Science Laboratories, Inc.

9:25

1-3
Device Technology Innovation for Exascale Computing
Invited T.C. Chen, IBM T. J. Watson Research Center
(Break 10:05-10:40)

Monday, June 15

Session 2A

Strain Engineering [Shunju I]
Chairpersons S. Takagi, The Univ. of Tokyo
O. Faynot, CEA-LETI

10:40

2A-1
Comparative Study Between Si (110) and (100) Substrates on Mobility and Velocity Enhancements for Short-Channel Highly-Strained PFETs
abstract   S. Mayuzumi*,**, S. Yamakawa*, D. Kosemura**, M. Takei**, K. Nagata**, H. Akamatsu**, K. Aamari*, Y. Tateshita*, H. Wakabayashi*, M. Tsukamoto*, T. Ohno*, M. Saitoh*, A. Ogura** and N. Nagashima*
*Sony Corporation and **Meiji University, Japan

11:05

2A-2
New Experimental Insight into Ballisticity of Transport in Strained Bulk MOSFETs
abstract D. Fleury*,**, G. Bidal*,**, A. Cros*, F. Boeuf*, T. Skotnicki* and G. Ghibaudo**
*STMicroelectronics, **IMEP-LAHC and ***Parvis Louis Néel, France

11:30

2A-3
Comprehensive Understanding of Surface Roughness Limited Mobility in Unstrained- and Strained-Si MOSFETs by Novel Characterization Scheme of Si/SiO2 Interface Roughness
abstract Y. Zhao*, H. Matsumoto**, T. Sato**, S. Koyama**, M. Takenaka* and S. Takagi*
*The University of Tokyo and **Hitachi High- Technologies Corporation, Japan

11:55

2A-4
Analyses and Optimization of Strained-SiGe on Si pMOSFETs by Using Full-Band Device Simulation
abstract H. Takeda*, M. Kawada**, K. Takeuchi* and M. Hane*
*NEC Electronics Corporation and **NEC Informatec Systems, Ltd, Japan
back to conference schedule
(Lunch 12:20-13:40)
Monday, June 15

Session 2B
Resistance Memory [Shunju II]
Chairpersons R. Yamada, Hitachi, Ltd.
F. Irrera, Sapienza Univ. of Rome

10:40

2B-1
Cross-Point Phase Change Memory with 4F² Cell Size Driven by Low-Contact-Resistivity Poly-Si Diode
abstract Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura and K. Torii
Hitachi, Ltd., Japan

11:05

2B-2
Vertical Cross-Point Resistance Change Memory for Ultra-High Density Non-Volatile Memory Applications
abstract H.S. Yoon, I.-G. Baek, J. Zhao, H. Sim, M.Y. Park, H. Lee, G.-H. Oh, J.C. Shin, I.-S. Yeo and U-I. Chung
Samsung Electronics Co. Ltd., Korea

11:30

2B-3
NiO Resistance Change Memory with a Novel Structure for 3D Integration and Improved Confinement of Conduction Path
abstract B. Lee and H.-S.P. Wong
Stanford University, USA

11:55

2B-4
Oxide-Based RRAM: Uniformity Improvement Using A New Material-Oriented Methodology
abstract B. Gao*, H.W. Zhang*, S. Yu*, B. Sun*, L.F. Liu*, X.Y. Liu*, Y. Wang*, R.Q. Han*, J.F. Kang*, B. Yu** and Y.Y. Wang*
*Peking University, China and **State University of New York, USA
back to conference schedule
(Lunch 12:20-13:40)
Monday, June 15

Session 3A

Advanced Gate Stack [Shunju I]
Chairpersons B.H. Lee, Gwangju Institute of Science and Technology
M. Khare, IBM Corp.

13:40

3A-1
Gate First High-k/Metal Gate Stacks with Zero SiOx Interface Achieving EOT=0.59nm for 16nm Application
abstract J. Huang*, D. Heh*, P. Sivasubramani**, P. D. Kirsch*, G. Bersuker*, D. C. Gilmer*, M.A. Quevedo-Lopez**, M. M. Hussain*, P. Majhi***, P. Lysaght*, H. Park*, N. Goel***, C. Young*, C.S. Park*, C. Park*, M. Cruz*, V. Diaz*, P. Y. Hung*, J. Price*, H.-H. Tseng* and R. Jammy*
*SEMATECH, **Intel assignee and ***UT Dallas, USA

14:05

3A-2
Cost-Effective 28-nm LSTP CMOS Using Gate- First Metal Gate/High-k Technology
abstract T. Tomimatsu*, Y. Goto*, H. Kato*, M. Amma*, M. Igarashi*, Y. Kusakabe*, M. Takeuchi*, S. Ohbayashi**, S.Sakashita*, T. Kawahara*, M. Mizutani*, M. Inoue*, M. Sawada*, Y. Kawasaki*, S. Yamanari*, Y. Miyagawa*, Y. Takeshima*, Y. Yamamoto*, S. Endo*, T. Hayashi*, Y. Nishida*, K. Horita*, T. Yamashita*, H. Oda*, K. Tsukamoto*, Y. Inoue**, H. Fujimoto*, Y. Sato**, K. Yamashita**, R. Mitsuhashi**, S. Matsuyama**, Y. Moriyama**, K. Nakanishi**, T. Noda**, Y. Sahara**, N. Koike**, J. Hirase**, T. Yamada**, H. Ogawa** and M. Ogura**
*Renesas Technology Corp. and **Semiconductor Company, Panasonic Corporation, Japan

14:30

3A-3
Optimized Ultra-Low Thermal Budget Process Flow for Advanced High-K / Metal Gate First CMOS Using Laser-Annealing Technology
abstract C. Ortolland*, L.-Å. Ragnarsson*, P. Favia*, O. Richard*, C. Kerner*, T. Chiarella*, E. Rosseel*, Y. Okuno**, A. Akheyar***, J. Tseng****, J.-L. Everaert*, T. Schram*, S. Kubicek*, M. Aoulaiche*, M.J. Cho**,*****, P.P. Absil*, S. Biesemans* and T. Hoffmann*
*IMEC, **assignee at IMEC from Panasonic, ***Infineon, ****TMSC and *****KU Leuven, Belgium

14:55

3A-4
Impact of Area Scaling on Threshold Voltage Lowering in La-Containing High-k/Metal Gate NMOSFETs Fabricated on (100) and (110)Si
abstract M. Inoue*, Y. Satoh**, M. Kadoshima*, S. Sakashita*, T. Kawahara*, M. Anma*, R. Nakagawa**, H. Umeda*, S. Matsuyama**, H. Fujimoto** and H. Miyatake*
*Renesas Technology Corporation and **Panasonic Corporation, Japan

15:20

3A-5
pFET Vt Control with HfO2 /TiN/Poly-Si Gate Stack Using a Lateral Oxygenation Process
abstract E. Cartier*, M. Steen*, B. P. Linder*, T. Ando*, R. Iijima**, M. Frank*, J.S. Newbury*, Y. H. Kim*, F. R. McFeely*, M. Copel*, R. Haight*, C. Choi*, A. Callegari*, V. K. Paruchuri* and V. Narayanan*
*IBM Semiconductor Research and Development Center (SRDC) and **Toshiba America Electronic Components, Inc., USA
back to conference schedule
(Break 15:45-16:00)
Monday, June 15

Session 3B

Random Telegraph Noise and Shot Noise [Shunju II]
Chairpersons T. Hiramoto, The Univ. of Tokyo
T. Skotnicki, STMicroelectronics

13:40

3B-1
New Insights into Oxide Traps Characterization in Gate-All-Around Nanowire Transistors with TiN Metal Gates Based on Combined Ig-Id RTS Technique
abstract L. Zhang*, J. Zhuge*, R. Wang*, R. Huang*, C. Liu*, D. Wu*, Z. Kang*, D.-W. Kim**, D. Park** and Y. Wang*
*Peking University, China and **Samsung Electronics Co., Korea

14:05

3B-2
The First Observation of Shot Noise Characteristics in 10-nm Scale MOSFETs
abstract J. Jeon*, J. Lee*, J. Kim*, C. H. Park**, H. Lee***, H. Oh***, H.-K. Kang***, B.-G. Park* and H. Shin*
*Seoul National University, **Kwangwoon University and ***Samsung Electronics, Korea

14:30

3B-3
Increasing Threshold Voltage Variation Due to Random Telegraph Noise in FETs as Gate Lengths Scale to 20 nm
abstract N. Tega*, H. Miki*, F. Pagette***, D. J. Frank***, A. Ray***, M. J. Rooks***, W. Haensch*** and K. Torii**
*Hitachi America Ltd., **Hitachi Ltd. and ***T. J. Watson Research Center, IBM, USA

14:55

3B-4
A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process- Induced Strain Using Random Telegraph Noise Measurement
abstract M.H. Lin*, E.R. Hsieh*, S.S. Chung*, C.H. Tsai**, P.W. Liu**, Y.H. Lin**, C.T. Tsai** and G.H. Ma**
*National Chiao Tung University and **United Microelectronics Corporation (UMC), Taiwan

15:20

3B-5
Single-Charge-Based Modeling of Transistor Characteristics Fluctuations Based on Statistical Measurement of RTN Amplitude
abstract K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai and Y. Hayashi
NEC Electronics Corporation, Japan
back to conference schedule
((Break 15:45-16:00)
Monday, June 15

Session 4A

Focus Session-3D System Integration [Shunju I]
Chairpersons T. Tanaka, Tohoku Univ.
R. Jammy, SEMATECH

16:00

4A-1
3D Integration for Energy Efficient System Design
Invited S. Borkar, Intel Corp.

16:25

4A-2
Process-Design Considerations for Three Dimensional Integration
Invited S. S. Iyer, IBM Corp.

16:50

4A-3
New 3D Integration Technology and 3D System LSIs
Invited M. Koyanagi, Tohoku Univ.

17:15

4A-4
3D System Integration
Invited S. Arkalgud, SEMATECH

17:40

4A-5
3D-LSI and System
Invited W.-C. Lo, ITRI
back to conference schedule

Monday, June 15

Session 4B

Ge MOSFET [Shunju II]
Chairpersons K. Shibahara, Hiroshima Univ.
K. Schruefer, Infineon Technologies AG

16:00

4B-1
Vth Variation and Strain Control of High Ge% Thin SiGe Channels by Millisecond Anneal Realizing High Performance pMOSFET Beyond 16nm Node
abstract S-H. Lee*,******, J. Huang*, P. Majhi*,**, P.D. Kirsch*, B-G. Min***, C-S. Park*, J. Oh*, W-Y. Loh*, C.-Y. Kang*, B. Sassman*, P.Y. Hung*, S. McCoy****, J. Chen****, B. Wu*****, G. Moori*****, D. Heh*, C. Young*, G. Bersuker*, H-H. Tseng*, S.K. Banerjee****** and R. Jammy*
* SEMATECH, **Intel, ***Jusung Engineering, ****Mattson Engineering, *****Poongsan Engineering and ******The University of Texas, USA

16:25

4B-2
High Quality GeO2/Ge Interface Formed by SPA Radical Oxidation and Uniaxial Stress Engineering for High Performance Ge NMOSFETs
abstract M. Kobayashi*, T. Irisawa*, B.M. Kope*, Y. Sun**, K. Saraswat*, H.-S.P. Wong*, P. Pianetta** and Y. Nishi*
*Stanford University and **Stanford Liner Accelerator Center, USA

16:50

4B-3
New Approach to Form EOT-Scalable Gate Stack with Strontium Germanide Interlayer for High-k/ Ge MISFETs
abstract Y. Kamata*, A. Takashima**, Y. Kamimuta* and T. Tezuka*
*MIRAI-Toshiba and **Toshiba Corporation, Japan

17:15

4B-4
Physical Origins of Mobility Enhancement of Ge pMISFETs with Si Passivation Layers
abstract N. Taoka*, W. Mizubayashi*, Y. Morita*, S. Migita*, H. Ota* and S. Takagi*,**
*MIRAI-NIRC, AIST and **The University of Tokyo, Japan

17:40

4B-5
Impact of EOT Scaling Down to 0.85nm on 70nm Ge-pFETs Technology with STI
abstract J. Mitard*,****, C. Shea*****, B. DeJaeger*, A. Pristera******, G. Wang*,****, M. Houssa****, G. Eneman*,*******, G. Hellings*,********, W-E. Wang**, J.C. Lin***, F.E. Leys*, R. Loo*, G. Winderickx*, E. Vrancken*, A. Stesmans****, K. DeMeyer*,****, M. Caymax*, L. Pantisano*, M. Meuris* and M. Heyns*,****
*IMEC, Bergium, **Intel, USA, ***TSMC, Taiwan, ****KULeuven, Bergium, *****Rochester Institute of Technology, USA, ******Univ. Calabria, Italy, *******FWO and ********IWT, Bergium
back to conference schedule
Monday, June 15
20:00

Rump Sessions
Organizers Y. Akasaka, Tokyo Electron Ltd.
K. Schruefer, Infineon Technologies AG

J-R

Is TSV 3D LSI’s and Packaging Finally Ready or Is It Just Another Fantasy? [Suzaku I, II]

Organizers

M. Takamiya, The Univ. of Tokyo
M. Clinton, Texas Instruments, Inc.
K. Schruefer, Infineon Technologies AG
K-W. Lee, Tohoku Univ.

Moderators

M. Koyanagi, Tohoku Univ.
S. Arkalgud, SEMATECH

Panelists
S. Borkar, Intel Corp.
J. Knickerbocker, IBM Corp.
L. Durodami, Qualcomm, Inc.
T. Kuroda, Keio Univ.
C. Berry, Amkor Technology
B. Haba, Tessera Inc.

3D LSI integration and packaging have been discussed for decades. Is TSV just the latest buzz-word or will it become a mainstream process? The panel will discuss which applications (memory, processor, memory+processor, imager, mixed-signal, FPGA or others) are driving the development of TSV and what types of applications could benefit from TSV in the future. The panel will debate how these applications get an advantage in the marketplace from TSV, which they cannot get from other 3D LSI integration or packaging technologies in manufacturing today.

We have assembled a distinguished panel of experts who will discuss and debate these questions and more as they explore the prospects of TSV for 3D LSI and packaging.

- Does TSV offer design, test, performance, yield, thermal / power or cost advantages over existing 3D technologies?
- What are main challenges and limitations for the acceptance in mainstream applications?
- Who will offer TSV as a design solution; IDM’s, Foundries and/or OSAT’s?


R-1

The Path Towards Sub 30nm Non Volatile Memories [Shunju I]

Moderators
R. Shirota, National Tsing Hua Univ.
J. Van Houdt, IMEC

Panelists

K. Schuegraf, SanDisk Corp.
C.H. Lam, IBM Corp.
H.-S. P. Wong, Stanford Univ .
S. Choi, Samsung Electronics Co., Ltd.
A. Nitayama, Toshiba Corp.
R. Liu, Macronix International Co., Ltd.
  In recent years, the demand for large density non-volatile memory has increased dramatically. This is mainly due to the tremendous growth in the market of portable devices which require large quantities of low-power (hence, preferably non-volatile) memory, such as digicam’s, MP3 players, USB sticks, cell phones, PDA’s etc. However, the enormous success of Flash memory technology in realizing multi-gigabyte memory chips has evidently triggered a lot of questions concerning its further scalability towards the sub-30nm nodes. Unlike DRAMs which densities are in most cases limited by choices made in PC architectures, the demand for ever-higherdensity Flash has no intrinsic upper limit. But can we project the roadmaps all the way down to 16nm without a fundamental change of concept? Assuming litho capabilities and high-k blocking layers will be available on time, we still have to deal with increasing interference between the charges that represent the binary information (in fact, today even smaller fractions of charges are already used in multilevel programming). Also, the absolute value of these charges becomes quite small and of the order of a few electrons. One obvious way out of these issues is to switch to a resistance-based concept such as phase change memory (PCM) or Resistance RAM (RRAM) but can these provide the same scalability and at what price? Or should we opt for 3D solutions on chip instead? These questions will be put forward and will serve as a starting point for a debate between a selected panel of experts with leading roles in the memory business.

R-2

Key Technology Options for 16nm CMOS and Beyond – Breaking the Barriers [Shunju II]

Moderators

Y. Toyoshima, Toshiba Corp.
T. Skotnicki, STMicroelectronics

Panelists
R. Jammy, SEMATECH
O. Faynot, CEA-LETI
W. Haensch, IBM Corp.
K. Kita, The Univ. of Tokyo
K. Uchida, Tokyo Institute of Technology
C. Wann, TSMC

When scaling down CMOS technology towards the 16nm node, the semiconductor community is facing serious challenges. At the 32nm node continued scaling for high performance and low power CMOS technologies have been achieved with the introduction of immersion lithography combined with double patterning and resolution enhancement techniques, multiple highly optimized and additive strain techniques, and the biggest innovation since 40 years of CMOS scaling, that certainly is high-k gate dielectric and metal gate. Today, the trends in research and development indicate that at the 22nm node existing solutions will be finally further scaled and optimized, and some new still evolutionary features like Si:C material for source/drain introduced to improve device performance and scaling.

For 16nm it is expected that controlling power and variability and simultaneously improving circuit performance will become the biggest challenge. Since the further scaling of the high-k / metal gate stack imposes fundamental problems as well as strain techniques are approaching their limit, the use of new device architectures such as ultra thin body SOI, Multi-Gate FET for short channel effect control or even alternative high mobility channel materials as performance boosters are possibly required. In this regard, the 16nm node may be the revolutionary and for a long time predicted departure from the “conventional” CMOS technology scaling. As a consequence, the technology options will have an increasing impact on circuit design and layout techniques.

This panel discussion will address the key technology challenges as well as enabling options for scaling down CMOS devices towards 16nm node. Which 16nm transistor structures are the most viable for logic and SRAM application? What determines the transistor architecture – density, performance, power, variability, complexity, manufacturability? What are the emerging challenges with device parasitics? What are the potential solutions in Lithography and how do they impact the transistor architecture? Finally, how do the different technology solutions (including new device architectures, immersion and EU lithography, double patterning and resolution enhancement techniques) impact circuit design and chip layout?

The distinguished panelist will also give an outlook on the viability of the technology solutions being discussed to extend Moore’s Law beyond the 16nm node towards the end of the roadmap.


Tuesday, June 16

Session 5A

Nanowire FETs [Shunju I]
Chairpersons S. Hayashi, Panasonic Corp.
W. Xiong, Texas Instruments, Inc.

8:30

5A-1
High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI
abstract J. Chen, T. Saraya and T. Hiramoto
The University of Tokyo, Japan

8:55

5A-2
Gate-All-Around Quantum-Wire Field-Effect Transistor with Dopant Segregation at Metal- Semiconductor-Metal Heterostucture
abstract H.-S. Wong*,**, L.-H. Tan**, L. Chan***, G.-Q. Lo**, G. Samudra* and Y.-C. Yeo*
*National University of Singapore, **Institute of Microelectronics and ***Chartered Semiconductor Manufacturing Ltd, Singapore

9:20

5A-3
Sub-10 nm Gate-All-Around CMOS Nanowire Transistors on Bulk Si Substrate
abstract M. Li, K.H. Yeo, S.D. Suk, Y.Y. Yeoh, D.-W. Kim, T.Y. Chung, K.S. Oh and W.-S. Lee
Samsung Electronics Co. Ltd., Korea

9:45

5A-4
A Novel Thin BOX SOI Technology Using Bulk Si Wafer for System-on-Chip (SoC) Application
abstract C.W. Oh, H.J. Bae, J.K. Ha, S.J. Park, B.K. Park, D.-W. Kim, T.Y. Chung, K.S. Oh and W.-S. Lee
Samsung Electronics Co., Korea
back to conference schedule
(Break 10:10-10:30)
Tuesday, June 16

Session 5B

Source / Drain Contact Technology [Shunju II]
Chairpersons Y. Akasaka, Tokyo Electron Ltd.
M. Mueller, NXP Semiconductors

8:30

5B-1
Selective Phase Modulation of NiSi Using N-Ion Implantation for High Performance Dopant- Segregated Source/Drain n-Channel MOSFETs
abstract W.-Y Loh*, P.Y. Hung*, B.E. Coss*, P. Kalra*, I. Ok*, G. Smith*, C.-Y. Kang*, S.-H. Lee***, J. Oh*, B. Sassman*, P. Majhi**, P. Kirsch*, H-H. Tseng* and R. Jammy*
*SEMATECH, **Intel assignee. and ***Univ. of Texas, USA

8:55

5B-2
Ultimate Contact Resistance Scaling Enabled by an Accurate Contact Resistivity Extraction Methodology for Sub-20 nm Node
abstract H.-N. Lin, W.-W. Hsu, W.-C. Lee and C.H. Wann
Taiwan Semiconductor Manufacturing Company Ltd., Taiwan

9:20

5B-3
CMOS Band-Edge Schottky Barrier Heights Using Dielectric-Dipole Mitigated (DDM) Metal/Si for Source/Drain Contact Resistance Reduction
abstract B.E. Coss*,**** W.-Y. Loh*, J. Oh*, G. Smith*, C. Smith*, H. Adhikari**, B. Sassman*, S. Parthasarathy*,*****, J. Barnett*, P. Majhi***, R.M. Wallace****, J. Kim**** and R. Jammy*
*SEMATECH, **AMD assignee, ***Intel assignee, ****Univ. of Texas at Dallas and *****Univ. of Florida, USA

9:45

5B-4
Single Silicide Comprising Nickel-Dysprosium Alloy for Integration in p- and n-FinFETs with Independent Control of Contact Resistance by Aluminum Implant
abstract M. Sinha*,**, R.T.P. Lee*, S.N. Devi*, G.-Q. Lo**, E.F. Chor* and Y.-C. Yeo*
*National University of Singapore (NUS) and **Institute of Microelectronics, Singapore
back to conference schedule
(Break 10:10-10:30)
Tuesday, June 16

Session 6A

Variability I [Shunju I]
Chairpersons M. Masahara, AIST
T.-J.King Liu, Univ. of California, Berkeley

10:30

6A-1
Analysis of Extra VT Variability Sources in NMOS Using Takeuchi Plot
abstract T. Tsunomura*, A. Nishida*, F. Yano*, A.T. Putra***, K. Takeuchi*, S. Inaba*, S. Kamohara*, K. Terada**, T. Mama***, T. Hiramoto*,*** and T. Mogami*
*MIRAI-Selete, **Hiroshima City University and ***The University of Tokyo, Japan

10:55

6A-2
Impact of Uniaxial Strain on Channel Backscattering Characteristics and Drain Current Variation for Nanoscale PMOSFETs
abstract W. Lee*, J.J.-Y. Kuo*, W.P.-N. Chen*, P. Su* and M.-C. Jeng**
*National Chiao Tung University and **Taiwan Semiconductor Manufacturing Company Ltd., Taiwan

11:20

6A-3
Physical Understanding of Vth and Idsat Variations in (110) CMOSFETs
abstract M. Saitoh*, N. Yasutake*, Y. Nakabayashi*, K. Uchida** and T. Numata*
*Toshiba Corporation and **Tokyo Institute of Technology, Japan

11:45

6A-4
A New Methodology for Evaluating VT Variability Considering Dopant Depth Profile
abstract A.T. Putra*, T. Tsunomura**, A. Nishida**, S. Kamohara**, K. Takeuchi**, S. Inaba**, K. Terada*** and T. Hiramoto*,**
*The University of Tokyo, **MIRAI-Selete and ***Hiroshima City University, Japan

12:10

6A-5
Comprehensive Analysis of Variability Sources of FinFET Characteristics
abstract T. Matsukawa, S. O’uchi, K. Endo, Y. Ishikawa, H. Yamauchi, Y.X. Liu, J. Tsukada, K. Sakamoto and M. Masahara
Nanoelectronics Research Institute, AIST, Japan
back to conference schedule
(Lunch 12:35-13:55)
Tuesday, June 16

Session 6B

Special Session-Beyond CMOS [Shunju II]
Chairpersons T. Hiramoto, The Univ. of Tokyo
A. Seabaugh, Notre Dame University

10:30

6B-1
Hybrid CMOS/Magnetic Tunnel Junction Approach for Nonvolatile Integrated Circuits
Invited H. Ohno, Tohoku Univ.

10:55

6B-2
Graphene Nanostructures for Device Applications
Invited J. Appenzeller, Purdue Univ.

11:20

6B-3
Gate Modulation of Graphene Contacts – on the Scaling of Graphene FETs
abstract Z. Chen* and J. Appenzeller**
*IBM T.J. Watson Research Center and **Purdue University, USA

11:45

6B-4
Nonvolatile Solid-Electrolyte Switch Embedded Into Cu Interconnect
abstract T. Sakamoto*, M. Tada*, N. Banno*, Y. Tsuji*, Y. Saitoh*, Y. Yabe*, H. Hada*, N. Iguchi* and M. Aono**
*NEC Corp. and **MANA, NIMS, Japan
12:10
6B-5
Collective-Effect State Variables for Post-CMOS Logic Applications
abstract A. Chen*, A.P. Jacob**, C.Y. Sung***, K.L. Wang****, A. Khitun**** and W. Porod*****
*Advanced Micro Devices, **Intel Corporation, ***IBM T J. Watson Research Center, ****University of California, Los Angeles and *****University of Notre Dame, USA
back to conference schedule
(Lunch 12:35-13:55)
Tuesday, June 16

Session 7

Highlights [Shunju I, II]
Chairpersons S.S. Chung, National Chiao Tung Univ.
K. Schruefer, Infineon Technologies AG

13:55

7-1
Pipe-Shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices
abstract R. Katsumata*, M. Kito*, Y. Fukuzumi*, M. Kido*, H. Tanaka*, Y. Komori*, M. Ishiduki*, J. Matsunami*, T. Fujiwara*, Y. Nagata***, L. Zhang**, Y. Iwata*, R. Kirisawa*, H. Aochi* and A. Nitayama*
*Toshiba Corporation, Semiconductor Company,**Toshiba Corporation and ***Toshiba Information Systems (Japan) Corporation, Japan

14:20

7-2
Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond
abstract K. Choi*, H. Jagannathan**, C. Choi***, L. Edge**, T. Ando***, M. Frank***, P. Jamison***, M. Wang***, E. Cartier***, S. Zafar***, J. Bruley***, A. Kerber*, B. Linder***, A. Callegari***, Q. Yang***, S. Brown***, J. Stathis***, J. Iacoponi*, V. Paruchuri** and V. Narayanan***
*Advanced Micro Devices, Inc., **IBM Research Division and ***IBM Research Division, T.J. Watson Research Center, USA

14:45

7-3
High Performance 32nm SOI CMOS with Highk/ Metal Gate and 0.149μm² SRAM and Ultra Low-k Back End with Eleven Levels of Copper
abstract B. Greene*, Q. Liang*, K. Amarnath**, Y. Wang*, J. Schaeffer***, M. Cai*, Y. Liang*, S. Saroop*, J. Cheng**, A. Rotondaro*, S-J. Han*, R. Mo*, K. McStay*, S. Ku*, R. Pal**, M. Kumar*, B. Dirahoui*, B. Yang**, F. Tamweber*, W-H. Lee*, M. Steigerwalt*, H. Weijtmans**, J. Holt*, L. Black**, S. Samavedam***, M. Turner***, K. Ramani**, D. Lee**, M. Belyansky*, M. Chowdhury***, D. Aimé***, B. Min***, H. van Meer**, H. Yin*, K. Chan*, M. Angyal*, M. Zaleski***, O. Ogunsola*, C. Child**, L. Zhuang*, H. Yan*, D. Permana**, J. Sleight*, D. Guo*, S. Mittl*, D. Ioannou*, E. Wu*, M. Chudzik*, D-G. Park*, D. Brown**, S. Luning**, D. Mocuta*, E. Maciejewski*, K. Henson* and E. Leobandung*
*IBM Semiconductor Research and Development Center (SRDC), **Advanced Micro Devices Inc, ***Freescale Semiconductor, USA

15:10

7-4
Characteristics of sub 5nm Tri-Gate Nanowire MOSFETs with Single and Poly Si Channels in SOI Structure
abstract S.D. Suk, M. Li, Y.Y. Yeoh, K.H. Yeo, J. K. Ha, H. Lim, H.W. Park, D.-W. Kim, T.Y. Chung, K.S. Oh and W.-S. Lee
Samsung Electronics Co., Korea
back to conference schedule
(Break 15:35-16:10)
Tuesday, June 16

Session 8A

Variability II [Shunju I]
Chairpersons E. Morifuji, Toshiba Corp.
K. Parekh, Micron

16:10

8A-1
Comprehensive Design Methodology of Dopant Profile to Suppress Gate-LER-Induced Threshold Voltage Variability in 20nm NMOSFETs
abstract H. Fukutome*,****, Y. Hori**, L. Sponton***, K. Hosaka*, Y. Momiyama*, S. Satoh*, R. Gull***, W. Fichtner**** and T. Sugii*
*Fujitsu Microelectronics Limited.,
**Fujitsu Quality Laboratory, Japan, ***Synopsys Switzerland LLC and ****ETH Zurich, Switzerland

16:35

8A-2
Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors
abstract M. Suzuki, T. Saraya, K. Shimizu, T. Sakurai and T. Hiramoto
The University of Tokyo, Japan

17:00

8A-3
Low Voltage (Vdd~0.6 V) SRAM Operation Achieved by Reduced Threshold Voltage Variability in SOTB (Silicon on Thin BOX)
abstract R. Tsuchiya, N. Sugii, T. Ishigaki, Y. Morita, H. Yoshimoto, K. Torii and S. Kimura
Hitachi, Ltd., Japan

17:25

8A-4
Reduction of RTA-Driven Intra-Die Variation Via Model-Based Layout Optimization
abstract J.C. Scott*, O. Gluschenkov**, B. Goplen***, H. Landis***, E. Nowak***, F. Clougherty***, A. Mocuta**, T. Hook**, N. Zamdmer**, C.W. Lai****, M. Eller*****, D. Chidambarrao**, J. Yu**, P. Chang**, J. Ferris***, S. Deshpande**, Y. Li**, H. Shang**, G. Hefferon**, R. Divakaruni**, E. Crabbé** and X. Chen**
*IBM Almaden Research Center, **IBM Semiconductor Research and Development Center, ***IBM Systems and Technology Group, ****Chartered Semiconductor Manufacturing Limited and *****Infineon Technologies, USA
back to conference schedule
(Joint Dinner 19:00-21:00)

Tuesday, June 16

Session 8B

Advanced Source / Drain Engineering [Shunju II]
Chairpersons T. Yamashita, Renesas Technology Corp.
T. Skotnicki, STMicroelectronics

16:10

8B-1
Sophisticated Methodology of Dummy Pattern Generation for Suppressing Dislocation Induced Contact Misalignment on Flash Lamp Annealed eSiGe Wafer
abstract O. Fujii*, T. Sanuki*, Y. Oshiki*, T. Itani*, T. Kugimiya*, N. Nakamura*, M. Tamura**, T. Sato*, I. Mizushima*, H. Yoshimura*, M. Iwai* and F. Matsuoka*
*Toshiba Corporation and **Toshiba Information Systems Corporation, Japan

16:35

8B-2
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor (Si:C S/D-E)
abstract S.S. Chung*, E.R. Hsieh*, P.W. Liu**, W.T. Chiang**, S.H. Tsai**, T.L. Tsai**, R.M. Huang**, C.H. Tsai**, W.Y. Teng**, C.I. Li**, T.F. Kuo**, Y.R. Wang**, C.L. Yang**, C.T. Tsai**, G.H. Ma**, S.C. Chien** and S.W. Sun**
*National Chiao Tung University and **United Microelectronics Corporation (UMC), Taiwan

17:00

8B-3
26 nm Gate Length CMOSFETs with Aggressively Reduced Silicide Position by Using Carbon Cluster Co-Implanted Raised Source/Drain Extension Structure
abstract K. Yako, T. Yamamoto, K. Uejima, T. Hase and M. Hane
NEC Electronics Corp., Japan

17:25

8B-4
The Fabrication of Low Leakage Junction with Ultra Shallow Profile by the Combination Annealing of 10-ms Low Power and 2-ms High Power FLA
abstract T. Onizawa, S. Kato, T. Aoyama, K. Ikeda and Y. Ohji
Semiconductor Leading Edge Technologies, Japan
back to conference schedule
(Joint Dinner 19:00-21:00)

Wednesday, June 17

Session 9A

Process Technology [Shunju I]
Chairpersons C.H. Wann, TSMC
B.V. Schravendijk, Novellus Systems, Inc.

8:30

9A-1
GeOI and SOI 3D Monolithic Cell Integrations for High Density Applications
abstract P. Batude*, M. Vinet*, A. Pouydebasque*, C. Le Royer*, B. Previtali*, C. Tabone*,
L. Clavelier*, S. Michaud*, A. Valentian*, O. Thomas*, O. Rozeau*, P. Coudrain**,
C. Leyris**, K. Romanjek*, X. Garros*, L. Sanchez*, L. Baud*, A. Roman*, V. Carron*,
H. Grampeix*, E. Augendre*, A. Toffoli*, F. Allain*, P. Grosgeorges*, V. Mazzochi*,
L. Tosti*, F. Andrieu*, J.-M. Hartmann*, D. Lafond*, S. Deleonibus* and O. Faynot*
*CEA/LETI and **STMicroelectronics, France

8:55

9A-2
Scratch-Free Dielectric CMP Slurry with 5-nm Colloidal Ceria Abrasive
abstract D. Ryuzaki, Y. Hoshi, Y. Machii,
N. Koyama, H. Sakurai and T. Ashizawa
*Hitachi Chemical Co., Ltd., Japan

9:20

9A-3
Reliability of a 300-mm-Compatible 3DI Technology Based on Hybrid Cu-Adhesive Wafer Bonding
abstract R.R. Yu*, F. Liu*, R.J. Polastre*, K.-N. Chen*, X.H. Liu*, L. Shi*, E.D. Perfecto**, N.R. Klymko**, M.S. Chace**, T.M. Shaw*, D. Dimilia*, E.R. Kinser**, A.M. Young*, S. Purushothaman*, S.J. Koester* and W. Haensch*
*IBM T. J. Watson Research Center and **IBM Semiconductor Research and Development Center, USA

9:45

9A-4
Impact of Backside Cu Contamination in the 3D Integration Process
abstract K. Hozawa, K. Takeda and K. Torii
Hitachi, Ltd., Japan
back to conference schedule
(Break 10:10-10:30)
Wednesday, June 17

Session 9B

Non-classical Transisters [Shunju II]
Chairpersons Y. Mochizuki, NEC Corp.
K. Schruefer, Infineon Technologies AG

8:30

9B-1
Programming Characteristics of the Steep Turn- On/Off Feedback FET (FBFET)
abstract C.W. Yeung, A. Padilla, T.-J. King Liu and C. Hu
University of California, Berkeley, USA

8:55

9B-2
Germanium-Source Tunnel Field Effect Transistors with Record High ION/IOFF
abstract S.H. Kim, H. Kam, C. Hu and T.-J. King Liu
University of California, Berkeley, USA

9:20

9B-3
Possibilities for VDD = 0.1V Logic Using Carbon- Based Tunneling Field Effect Transistors
abstract Y. Gao, T. Low and M. Lundstrom
Purdue University, USA

9:45

9B-4
A Metallic-CNT-Tolerant Carbon Nanotube Technology Using Asymmetrically-Correlated CNTs (ACCNT)
abstract A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong
Stanford University, USA
back to conference schedule
(Break 10:10-10:30)
Wednesday, June 17
Session 10A
NAND Flash Memory [Shunju I]
Chairpersons S.S. Chung, National Chiao Tung Univ.
J. Lutze, Sandisk Corp.

10:30

10A-1
Novel Vertical-Stacked-Array-Transistor (VSAT) for Ultra-High-Density and Cost-Effective NAND Flash Memory Devices and SSD (Solid State Drive)
abstract J. Kim*, A.J. Hong*, S. Min Kim*, E.B. Song*, J.H. Park*, J. Han**, S. Choi**, D. Jang**, J.-T. Moon** and K.L.Wang*
*University of California, Los Angeles, USA and **Samsung Electronics Co., Korea

10:55

10A-2
Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage
abstract W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo and Y. Park
Samsung Electronics Co., LTD., Korea

11:20

10A-3
20nm-Node Planer MONOS Cell Technology for Multi-Level NAND Flash Memory
abstract T. Yaegashi*, T. Okamura*, W. Sakamoto*, Y. Matsunaga*, T. Toba*, K. Sakuma**, K. Gomikawa*, K. Komiya*, H. Nagashima*, H. Akahori*, K. Sekine*, T. Kai*, Y. Ozawa*, M. Sugi*, S. Watanabe*, K. Narita*, M. Umemura*, H. Kutsukake*, M. Sakuma*, H. Maekawa*, Y. Ishibashi*, K. Sugimae*, H. Koyama*, T. Izumida*, M. Kondo*, N. Aoki* and T. Watanabe*
*Semiconductor Company, Toshiba Corporation and **Advanced LSI Technology Laboratory, Toshiba Corporation, Japan

11:45

10A-4
Vertical Cell Array Using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory
abstract J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S.I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D.W. Kim, K. Kim, J.-J. Shim, J.S. Lim, K.-H. Kim, S.Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U-I. Chung and W.-S. Lee
Samsung Electronics Co. Ltd., Korea
back to conference schedule
(Lunch 12:35-14:20 *Circuits Luncheon Talk 12:45-14:05)

Wednesday, June 17
Session 10B
Special Session-Explorative Research [Shunju II]
Chairpersons Y. Mochizuki, NEC Corp.
T.-J. King Liu, Univ. of California, Berkeley

10:30

10B-1
Guiding Principles Toward Future Gate Stacks Given by the Construction of New Physical Concepts
Invited K. Shiraishi, Univ. of Tsukuba

10:55

10B-2
Applications of Advanced Transmission Electron Microscopy Techniques in Gate Stack Scaling
Invited S. Stemmer, Univ. of California, Santa Barbara

11:20

10B-3
Charged Defects Reduction in Gate Insulator with Multivalent Materials
abstract M. Kouda*, N. Umezawa**, K. Kakushima*, P. Ahmet*, K. Shiraishi***, T. Chikyow**, K. Yamada**** and H. Iwai*
*Tokyo Institute of Technology, **National Institute for Materials Science, ***University of Tsukuba and ****Waseda University, Japan

11:45

10B-4
Correlation Among Crystal Defects, Depletion Regions and Junction Leakage in Sub-30-nm Gate- Length MOSFETs: Direct Examinations by Electron Holography
abstract N. Ikarashi*, K. Yako**, K. Uejima**, T. Yamamoto**, T. Ikezawa*** and M. Hane**
*NEC Corporation, **NEC Electronics Corporation and ***NEC Informatec Systems Corporation, Japan

12:10

10B-5
A Direct Observation on the Structure Evolution of Memory-Switching Phenomena Using In-Situ TEM
abstract D. Cha*, S.J. Ahn**, S.Y. Park*, H. Horii**, D.H. Kim**, Y.K. Kim**, S.O. Park**, U.I. Jung**, M.J. Kim* and J. Kim*
*University of Texas at Dallas, USA and **Samsung Electronics Co, Korea
back to conference schedule
(Lunch 12:35-14:20 *Circuits Luncheon Talk 12:45-14:05)
Wednesday, June 17
Session 11A
CMOS Device Integration [Shunju I]
Chairpersons H. Wakabayashi, Sony Corp.
S. Biesemans, IMEC

14:20

11A-1
A Scalable and Highly Manufacturable Single Metal Gate/High-k CMOS Integration for Sub- 32nm Technology for LSTP Applications
abstract C.S. Park*, M.M. Hussain*, J. Huang*, C. Park*, K. Tateiwa**, C. Young*, H.K. Park*, M. Cruz*, D. Gilmer*, K. Rader*, J. Price*, P. Lysaght*, D. Heh*, G. Bersuker*, P.D. Kirsch*, H.-H. Tseng* and R. Jammy*
*SEMATECH and **Panasonic Assignee, USA

14:45

11A-2
A Highly Manufacturable 28nm CMOS Low Power Platform Technology with Fully Functional 64Mb SRAM Using Dual/Tripe Gate Oxide Process
abstract S.-Y. Wu, J.J. Liaw, C.Y. Lin, M.C. Chiang, C.K. Yang, J.Y. Cheng, M.H. Tsai, M.Y. Liu, P.H. Wu, C.H. Chang, L.C. Hu, C.I. Lin, H.F. Chen, S.Y. Chang, S.H. Wang, P.Y. Tong, Y.L. Hsieh, K.H. Pan, C.H. Hsieh, C.H. Chen, C.H. Yao, C.C Chen, T.L. Lee, C.W. Chang, H.J. Lin, S.C. Chen, J.H. Shieh, M.H. Tsai, S.M. Jang, K.S. Chen, Y. Ku, Y.C. See and W.J. Lo
Taiwan Semiconductor Manufacturing Company, Taiwan

15:10

11A-3
Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain
abstract K. Cheng*, A. Khakifirooz*, P. Kulkarni*, S. Kanakasabapathy*, S. Schmitz*, A. Reznicek*, T. Adam*, Y. Zhu**, J. Li***, J. Faltermeier*, T. Furukawa*, L. F. Edge*, B. Haran*, S.-C. Seo*, P. Jamison*, J. Holt***, X. Li***, R. Loesing***, Z. Zhu***, R. Johnson*, A. Upham*, T. Levin*, M. Smalley*, J. Herman*, M. Di*, J. Wang*, D. Sadana**, P. Kozlowski*, H. Bu*, B. Doris* and J. O’Neill*
*IBM Research at Albany Nanotech, **IBM T.J. Watson Research Center and ***IBM Semiconductor Research and Development Center, USA

15:35

11A-4
The Study of Mobility-Tinv Trade-off in Deeply Scaled High-k / Metal Gate Devices and Scaling Design Guideline for 22nm-Node Generation
abstract M. Goto, S. Kawanaka, S. Inumiya, N. Kusunoki, M. Saitoh, K. Tatsumura, A. Kinoshita, S. Inaba and Y. Toyoshima
Toshiba Corporation, Japan
back to conference schedule
(Break 16:00-16:15)
Wednesday, June 17
Session 11B
Novel Memory [Shunju II]
Chairpersons S. Ohnishi, Sharp Corp.
K.-M. Chang, Freescale

14:20

11B-1
High-Density and High-Speed 128Mb Chain FeRAMTM with SDRAM-Compatible DDR2 Interface
abstract Y. Shimojo, A. Konno, J. Nishimura, T. Okada, Y. Yamada, S. Kitazaki, H. Furuhashi, S. Yamazaki, K. Yahashi, K. Tomioka, Y. Minami, H. Kanaya, S. Shuto, K. Yamakawa, T. Ozaki, H. Shiga, T. Miyakawa, S. Shiratake, D. Takashima, I. Kunishima, T. Hamamoto and A. Nitayama
Semiconductor Company, Toshiba Corporation, Japan

14:45

11B-2
Parallel Multi-Confined (PMC) Cell Technology for High Density MLC PRAM
abstract G.H. Oh, Y.L. Park, J.I. Lee, D.H. Im, J.S. Bae, D.H. Kim, D.H. Ahn, H. Horii, S.O. Park, H.S. Yoon, I.S. Park, Y.S. Ko, U-In. Chung and J.T. Moon
Samsung Electronics Co., Ltd., Korea
15:10
11B-3
Performance Breakthrough in NOR Flash Memory with Dopant-Segregated Schottky-Barrier (DSSB) SONOS Devices
abstract S.-J. Choi*, J.-W. Han*, S. Kim*, D.-I. Moon*, M.-G. Jang**, J.S. Kim***, K.H. Kim***, G.S. Lee***, J.S. Oh***, M.H. Song***, Y.C. Park***, J.W. Kim*** and Y.-K. Choi*
*KAIST, **ETRI and ***National Nanofab Center, Korea

15:35

11B-4
A Novel Buried-Channel FinFET BE-SONOS NAND Flash with Improved Memory Window and Cycling Endurance
abstract H.-T. Lue, Y.-H. Hsiao, P.-Y. Du, S.-C. Lai, T.-H. Hsu, S.P. Hong, M.T. Wu, F.H. Hsu, N.Z. Lien, C.-P. Lu, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu and C.-Y. Lu
Macronix International Co., Ltd., Taiwan
back to conference schedule
(Break 16:00-16:15)
Wednesday, June 17
Session 12A
Floating Body DRAM and MRAM [Shunju I]
Chairpersons S. Ohnishi, Sharp Corp.
W. Mueller, Qimonda

16:15

12A-1
SPRAM with Large Thermal Stability for High Immunity to Read Disturbance and Long Retention for High-Temperature Operation
abstract K. Ono*, T. Kawahara*, R. Takemura*, K. Miura*, M. Yamanouchi*, J. Hayakawa*, K. Ito*, H. Takahashi*, H. Matsuoka*, S. Ikeda** and H. Ohno**
*Hitachi, Ltd. and **Tohoku University, Japan

16:40

12A-2
Low-Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM
abstract S. Fukami*, T. Suzuki*, K. Nagahara*, N. Ohshima*, Y. Ozaki**, S. Saito*, R. Nebashi*, N. Sakimura*, H. Honjo*, K. Mori*, C. Igarashi*, S. Miura*, N. Ishiwata* and T. Sugibayashi*
*NEC Corporation and **NEC Electronics Corporation, Japan

17:05

12A-3
Vertical Capacitor-less Thyristor Cell for 30nm Stand-Alone DRAM
abstract S. Slesazeck*, J. Holz*, R. Hagenbeck**, A. Milia*, G. Guerrero*, J. Hartwich* and W. Mueller*
*Qimonda Dresden GmbH & Co. OHG and **Qimonda AG, Germany

17:30

12A-4
Highly Scalable Z-RAM with Remarkably Long Data Retention for DRAM Application
abstract T.-S. Jang*, J.-S. Kim*, S.-M. Hwang*, Y.-H. Oh*, K.-M. Rho*, S.-J. Chung*, S.-O. Chung*, J.-G. Oh*, S. Bhardwaj**, J. Kwon**, D. Kim**, M. Nagoga**, Y.-T. Kim*, S.-Y. Cha*, S.-C. Moon*, S.-W. Chung*, S.-J. Hong* and S.-W. Park*
*Hynix Semiconductor Inc., Korea and **Innovative Silicon Inc., USA
back to conference schedule
Wednesday, June 17
Session 12B
High Mobility Devices [Shunju II]
Chairpersons H. Kurata, Fujitsu Laboratories Ltd.
R. Jammy, SEMATECH

16:15

12B-1
Mechanisms for Low On-State Current of Ge (SiGe) nMOSFETs: A Comparative Study on Gate Stack, Resistance, and Orientation-Dependent Effective Masses
abstract J. Oh*, I. Ok*, C.-Y. Kang*, M. Jamil**, S.-H. Lee**, W.-Y. Loh*, J. Huang*, B. Sassman,* L. Smith***, S. Parthasarathy****, B. E. Coss*****, W.-H. Choi******, H.-D. Lee******, M. Cho*******, S.K. Banerjee**, P. Majhi*, P.D. Kirsch*, H.-H. Tseng* and R. Jammy*
*SEMATECH, **Univ. of Texas at Austin, ***Synopsys, ****Univ. of Florida, *****Univ. of Texas at Dallas, ******Chungnam National Univ. and *******GIST, USA

16:40

12B-2
High Velocity Si-Nanodot : A Candidate for SRAM Applications at 16nm Node and Below
abstract G. Bidal*,**, F. Boeuf*, S. Denorme*, N. Loubet*, J.L. Huguenin*,**, P. Perreau***, D. Fleury*,**, F. Leverd*, S. Lagrasta*, S. Barnola***, T. Salvetat*** , B. Orlando*, R. Beneyton*, L. Clement*, R. Pantel*, S. Monfray*, G. Ghibaudo** and T. Skotnicki*
*STMicroelectronics, **IMEP, Minatec INPG and ***CEA-LETI/Minatec, France

17:05

12B-3
High Mobility Metal S/D III-V-On-Insulator MOSFETs on a Si Substrate Using Direct Wafer Bonding
abstract M. Yokoyama*, T. Yasuda**, H. Takagi**, H. Yamada***, N. Fukuhara***, M. Hata***, M. Sugiyama*, Y. Nakano*, M. Takenaka* and S. Takagi*
*The University of Tokyo, **National Institute of Advanced Industrial Science and Technology and ***Sumitomo Chemical Co. Ltd., Japan

17:30

12B-4
Strained In0.53 Ga0.47As n-MOSFETs: Performance Boost with in-situ Doped Lattice-Mismatched Source/Drain Stressors and Interface Engineering
abstract H.-C. Chin, X. Gong, X. Liu, Z. Lin and Y.-C. Yeo.
National University of Singapore (NUS), Singapore
back to conference schedule


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