Abstract: The short course provides a design-centric treatment of ultra-low voltage logic circuits for operation at nearly minimum energy. The challenges posed by aggressive voltage scaling are discussed, and design guidelines to achieve robust/energy-efficient operation are presented. Quantitative tools are introduced to make quick estimates and design decisions at circuit level, and evaluate the impact at adjacent levels. Several academic and industrial designs are presented to gain an insight into the tradeoff between energy, performance and resiliency. Emphasis is given on design issues and solutions that significantly depart from the (often wrong) common wisdom that comes from traditional (above-threshold) designs.
Bio: Massimo Alioto received the Laurea and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001. He is currently an Associate Professor at the Electrical and Computer Engineering Department of the National University of Singapore and previously held various positions, including Associate Professor at University of Siena, Visiting Scientist at Intel Labs – CRL (2013), Visiting Professor at University of Michigan – Ann Arbor (2011-2012), BWRC – University of California, Berkeley (2009-2011), EPFL (2007). He co-authored 180+ journal/conference publications and two books. His research interests include ultra-low voltage VLSI circuits, green computing, self-powered sub-uW systems, error-aware and widely energy-scalable VLSI circuits, emerging technologies. He was IEEE Distinguished Lecturer (2010-2012) and Chair of the “VLSI Systems and Applications” Technical Committee (2011-2012). He is Associate Editor in Chief of IEEE Transactions on VLSI Systems, and served as Guest Editor of various journal special issues. He serves as Associate Editor of several journals (including ACM TODAES and IEEE TCAS-I), and he was Technical Program Chair (ICECS 2013, NEWCAS 2012, ICM 2010) and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM).