2012 VLSI Circuits Short Course Program
“Designing in Advanced CMOS Technologies”
Tuesday, June 12, 2012
Chairs: |
Andreia Cathelin, STMicroelectronics
Masato Motomura, Hokkaido University |
8:30 a.m. |
Introduction
Andreia Cathelin, STMicroelectronics |
| 8:45 a.m. |
Bulk CMOS Scaling to the End of the Roadmap
Tsu-Jae King Liu, University of California, Berkeley |
| 9:45 a.m. |
Technology Boosters for LP Design Platforms in 28/20nm
Thomas Skotnicki, STMicroelectronics |
| 10:45 a.m. |
Break |
| 11:00 a.m. |
Challenges and Solutions Paths in Scaling SRAM
Fatih Hamzaoglu, Intel |
| 12:00 p.m. |
Lunch |
| 1:00 p.m. |
The Mixed-Signal Design Challenges in the Advanced Technology Nodes
Fu-Lung Hsueh, TSMC |
| 2:00 p.m. |
Power-aware Design in 28nm Generation and Beyond-Facts, Myths, and Misunderstandings
Youngsoo Shin, KAIST
|
| 3:00 p.m. |
Break |
| 3:15 p.m. |
Advanced CAD Methodologies for Custom Design at Advanced Process Nodes
David White, Cadence |
| 4:15 p.m. |
Round Table Discussion
All Speakers |
2012 VLSI Circuits Short Course 2
“Ultra Low Power SoC Design for Future Mobile Systems”
Tuesday, June 12, 2012
Chairs: |
Alice Wang, MediaTek
Koichi Nose, Renesas Electronics Corp. |
8:10 |
Introduction
Alice Wang, MediaTek |
| 8:45 a.m. |
Vision of Future Mobile Systems
Jan Rabaey, Univ. of California, Berkeley |
| 9:45a.m. |
Low-Power Logic Design Technologies
Masaya Sumita, Panasonic |
| 10:45 a.m. |
Break |
| 11:00 a.m. |
Memory Architecture and Systems for Mobile Systems
Kyomin Sohn Samsung |
| 12:00 p.m. |
Lunch |
| 1:00 p.m. |
Wireless Communication
Gangadhar Burra, Texas Instruments |
| 2:00 p.m. |
Interconnect and Wireline Communication
Jared Zerbe, Rambus |
| 3:00 p.m. |
Break |
| 3:15 p.m. |
Case-Study on Low-Power Mobile System
John Redmond, Broadcom |
| 4:15 p.m. |
Round Table Discussion
All Speakers |
|
