Best Student Paper Award Committees


Welcome to the 2012 Symposium on VLSI Technology

PDFPDF of Advance Program (as of May 21)

We would like to cordially welcome you to the 2012 Symposium on VLSI Technology to be held from June 12-14 at the Hilton Hawaiian Village in Honolulu, Hawaii. The VLSI Symposium has long been recognized as one of the premiere technical conferences introducing the latest technology advancements in semiconductor microelectronics, with no exception this year.

A unique aspect of this conference is, following a long tradition, that it is held jointly with The Symposium on VLSI Circuits. The co-location of these two Symposia provides the excellent opportunity to span the whole range from process technology to System-on-Chip integration, and to promote interactions between technologists and circuit/system designers in an open forum.

Research results presented at the Symposium on VLSI Technology comprise a broad spectrum of VLSI technology topics, including new concepts and breakthroughs in VLSI materials, processes, devices, interconnects, and packaging up to 3D-system integration. Beyond advanced theories, fundamentals, characterization, analysis, modeling, and reliability for VLSI devices, heterogeneous integration of non-Si materials/devices on large Si substrates and new functional devices beyond CMOS with a path for VLSI implementation will be discussed.

In recent years, when collaboration among transistor, circuits, and systems designers became critical to innovation, this conference enables attendees to gain a broad understanding of the latest advances that will drive the industry forward. This year, we have focused on many areas of joint interest between technology and circuits to create an outstanding technical program that will allow attendees to experience the unique value of this shared location.

To offer attendees an exquisite opportunity to learn about the latest advances in semiconductor devices and memory technologies and their implications for VLSI circuit design, we will start the symposium with a one day Short Course on “14nm CMOS Technology and Design Co-optimization and Emerging Memory Technologies,” on June 11th. These courses, given by industry and academic leaders in their respective fields, will address state-of-the-art topics that have a huge impact on our industry and are of interest to both Technology and Circuits attendees.

This year we have 22 regular sessions with 91 outstanding papers comprising 13 invited papers, and, for the first time in 2012, joint Technology & Circuits Focus Sessions on design enablement in scaled CMOS technology, 3D-system integration, and advanced memory design & technology co-optimization. In addition, two Technology Focus Sessions comprising invited and regular papers will cover low power and steep sub-threshold technology (Tunnel FETs, Nano-electromechanical relays), and 3D-system integration (BEOL, far-BEOL, TSV).

We invited two distinguished plenary speakers to present recent advances and new challenges related to VLSI technologies and applications. The Plenary Session on June 12th opens with “Peering through the Technology Scaling Fog,” presented by Mike Mayberry, Director of Component Research, Intel Corporation, and discusses the technology inflection points and choices that need to be made to be ready for technology in 2020 and beyond. The second talk is on “Wearable Sensing Systems for Healthcare Monitoring,” presented by I. Yamada, University of Tokyo. Dr. Yamada will present the recent development in wearable sensing systems for preventive healthcare monitoring made possible by revolutionary advances in micro-machine, LSI, and wireless technologies.

VLSI Technology Symposium evening Rump Sessions are well known for their selection of timely topics and enthusiastic discussions with technical leaders on the panel and in the audience. This year, we have again three Rump Sessions. The first one, “Scaling Challenges beyond 1x nm DRAM and NAND Flash,” is a joint session with the VLSI Circuits Symposium on the evening of June 12th. The remaining two sessions on the evening of June 12th are “Evolution of FinFET and beyond?” and “Patterning in non-planar world – EUV, DW or tricky-193?”.

We also have been organizing a luncheon talk for attendees of Circuits and Technology Symposia to enjoy informative and entertaining speeches on interesting topics in a relaxed atmosphere with excellent food. This year, it will feature the talk “Nano Satellites, CubeSats, and the Next Space Generation” by Prof. James Cutler from University of Michigan.

This year’s excellent technical program with an outstanding set of remarkable top quality paper has been compiled by the committee members, all world-wide leaders in the field of VLSI technologies. We are sure that you will enjoy the paper presentations, and we cordially invite you to participate in the lively discussions in and outside of the sessions and in an informal and convenient atmosphere.

This is a rich and exciting technical program, and we certainly hope that you will take advantage of the opportunities to network with your industrial and university colleagues between the technical sessions as well as have a productive and enjoyable experience.

We look forward to meeting with you at the Symposium in Honolulu

Klaus Schruefer

Toshiro Hiramoto
Program Chair Program Co-Chair


Sunday, 6/10


Monday, 6/11 7:30a-5:00p Registration
8:10a-5:15p Short Course
Tuesday, 6/12 7:30a-5:00p Registration
8:05a-10:10a Session 1 Opening and Plenary Session
10:25a-12:05p Session 2 Advanced Fin FET Devices and Technology
Session 3 NAND Flash
1:30p-3:10p Session 4 High-K / Metal Gate Scaling
Session 5 Alternative Memory
3:25p-5:30pSession 6 Low Power and Steep Subthreshold Technology
Session 7 STT MRAM
6:30p-7:30p Joint Technology / Circuits Reception
8:00p-10:00pRump Sessions
Wednesday, 6/13 7:30a-5:00p Registration
8:05a-10:10aC-Session 1 Circuits Opening and Plenary Session
Session 8 RRAM I
10:25a-12:05pSession 9 Process Technology
Session 10 Technology / Circuits Joint Focus Session – Memory
1:30p-3:10pSession 11 Mobility Enhancement
Session 12 Technology / Circuits Joint Focus Session – 3D-System Integration
3:25p-5:30pp C-Session 6 Technology/Circuits Joint Focus Session - Emerging Nonvolatile Memory
Session 13 Ultra-Thin Body Devices
Session 14 Novel Passive and Active BEOL Technologies
7:00p-9:00p Joint Technology/Circuits Banquet
Thursday, 6/14 8:00a-5:00p Registration
8:05a-9:45a C-Session 8 Technology/Circuit Joint Focus Session - Advanced SRAM
Session 15 CMOS Platform
Session 16 Noise Phenomena
10:00a-12:05pSession 17 Technology / Circuits Joint Focus Session – Design in Scaled Technologies
Session 18 RRAM II
12:05p-1:15p Technology and Circuits Joint Luncheon Talk
1:30p-3:10p C-Session 12 Technology/Circuit Joint Focus Session - Design Enablement in Scaled CMOS
Session 19 High Mobility – Ge Devices
Session 20 3D Integration Technology
3:25p-5:30p C-Session 14 Technology/Circuit Joint Focus Session - Embedded Memory
Session 21 Scaled III-V Transistors and Modeling
Session 22 Variability Characterization and Modeling

Call for papersTechnical ProgramShort CoursesCommitteesBest Student Paper Award