PLENARY & RUMP SESSIONS

Plenary and Rump Sessions

• Technology Plenary Session

  Tuesday, June 10, 2014

  “Device and Technology Implications of the Internet of Things”, Rob Aitken, Fellow, ARM

  We live in an interconnected world. Computing power once reserved for server rooms now resides in our pockets. Tablets now outsell PCs. As marked as these changes have been, we are now entering a new era of vastly greater connectivity, where people interact with the world around them in entirely new ways. The Internet of Things is in its infancy, so predictions of precisely what it will become are dangerous, but several things are clear. First, the leaf nodes of the network will share some device and technology properties in terms of cost and computing capability, but also analog and wireless functionality. These nodes will interact with people and with the cloud. The “little data” of these interactions needs to integrate seamlessly with the “big data” of the world around them. The trust, security and service components of these interactions lead to further device and technology requirements. This talk looks at the trends and discusses some likely paths forward.

  

  Robert Aitken, Fellow, ARM

  Robert Aitken is an ARM Fellow and heads the Silicon portion of ARM R&D. His areas of responsibility include low power design, library architecture for advanced process nodes, design/technology co-optimization, and advanced implementation techniques. His group has participated in numerous chip tape-outs, including 6 at or below the 16nm node. He holds numerous patents and has published over 70 technical papers, on a wide range of topics.  Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

  This talk focuses on the impact of the information explosion and semiconductor technology on consumer electronics and information industries. The progress of semiconductor technology under Moore’s Law and information transmission technology has eased various limitations for customers, such as place, time and preparations.  The television, the video recorder, and on-demand broadcasting are technologies that have helped to overcome these limitations and realize new customer values.

  The amount of communication is still rapidly growing due to the explosion of data contents (such as 4K) and data creators (such as CGM and IoT). This trend will create another industry and new customer values.

  

  Keiichiro Shimada, Senior Vice President, Sony Corporation

  Keiichiro Shimada is SVP Corporate Executive at Sony Corporation. He joined Sony in 1981 after he graduated from the Department of Electronics, The University of Tokyo. He was General Manager and President of VAIO Notebook Computer from 1996, President of Mobile Electronics Development Group and Deputy President of Digital Imaging Business Group from 2004, and President of Technology Development Group from 2006 to 2012. He was appointed SVP Corporate Executive in 2007, and in charge of R&D and Software Design from 2009 to 2012. He is currently in charge of Mid-to-Long Term Technology and Corporate Technology Policy & Relations.

  Mr. Shimada also contributes to the  JEITA (Japan Electronics and Information Technology Industries Association) and the Ministry of Internal Affairs and Communications, Japan.

• Circuits Plenary Session

  Wednesday, June 11, 2014

  “DataCenter 2020: Near-memory Acceleration for Data-oriented Applications”, Ed Doller, Vice President and Chief Memory Systems Architect, 
Micron

  In the years between now and 2020, we should expect continued exponential data growth.  A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe.  This will significantly reduce the ratio of storage bandwidth to storage density.  Consequently, the majority of data in 2020 will either be cold or will require near-memory acceleration to pull rich information out of the sea of big data.  We argue that, increasingly over time, value lies not merely in the size of the data, but rather in what one can do with it.

  “Technology development for printed LSIs based on organic semiconductors”,  Jun Takeya, Department of Advanced Materials and Science, School of Frontier Sciences, The University of Tokyo

  This presentation focuses on recent development of key technologies for printed LSIs which can provide future low-cost platforms for RFID tags, AD converters, data processors, and sensing circuitries. Such prospect bears increasing reality because of recent research innovations in the field of material chemistry, charge transport physics, and solution processes of printable organic semiconductors. Achieving band transport in state-of-the-art printable organic semiconductors, carrier mobility is elevated above 15 cm²/Vs, so that reasonable speed in moderately integrated logic circuits can be available. With excellent chemical and thermal stability for such compounds, we are developing simple integrated devices based on CMOS using p-type and n-type printed organic FETs. Particularly important are new processing technologies for continuous growth of inch-size organic single-crystalline semiconductor “wafers” from solution and for lithographical patterning of semiconductors and metal electrodes. Successful rectification and identification are demonstrated at 13.56 MHz with printed organic CMOS circuits for the first time.

  

  Ed Doller, Vice President and Chief Memory Systems Architect, 
Micron

  Ed Doller is Vice President and Chief Memory Systems Architect at Micron Technology. Mr. Doller joined Micron in May 2010 from Numonyx where he served as Chief Technology Officer after its formation in 2008. Before Numonyx, Mr. Doller had a variety of roles in the Flash memory group at Intel, and then was appointed its Chief Technology Officer in 2004. Prior to Intel, he held several key positions at IBM in East Fishkill, N.Y., all in advanced semiconductor memories.

  Mr. Doller earned a Bachelor of Science degree in computer engineering from Purdue University. He has 30 years of experience in semiconductor memories, holds multiple patents, is a co-author of the IEEE floating gate standard, and is a frequent keynote speaker at memory conferences.

  

  Jun Takeya, Professor in Graduate School of Frontier Sciences, The University of Tokyo

  Jun Takeya received his Ph.D. at the same university in 2001 when he was a research scientist in Central Research Institute of Electric Power Industry from 1991. He was an Associate Professor in Graduate School of Science at Osaka University from 2006 and was a Professor in Institute of Scientific and Industrial Research at the same university from 2010 before moving to the current position. His research interests lie in the area of material science and device physics of organic electronics.

• Joint Rump Session

  Technology / Circuits Joint Rump Session

  Tuesday, June 10, 8:00 pm – 10:00 pm

  Who gives up on scaling first: device and process technology engineers, circuit designers, or company executives?  Which scaling ends first – memory, or logic?

  Technology Organizers:
  C. Mazure, SOITEC and Y.C. Yeo, National University of Singapore

  Circuits Organizers:
  E. Alon, University of California, Berkeley and M. Yamaoka, Hitachi
  Moderators: E. Alon, University of California, Berkeley, Y.C. Yeo, National University of Singapore

  Panelists: 
  M. Bohr Intel
  M. Cao, TSMC
  J. Chen, Nvidia
  S-H Lee, Hynix
  T-J King Liu, University of California, Berkeley
  K. Nii, Renesas
  R. Shrivastava, Sandisk
  T. Skotnicki, STMicroelectronics
  E. Terzioglu, Qualcomm
  

  While many past predictions of the end of CMOS scaling were proven to be incorrect, there is now no question that the nature of scaling today has shifted dramatically.  In particular, energy, performance, and perhaps even cost no longer clearly/directly benefit from simple dimensional scaling.  This panel will therefore address the now extremely timely question of who will finally drive the decision to stop CMOS scaling, and why will they do so.  Will CMOS continue to scale as far as device and process engineers are able to develop cost-effective manufacturing infrastructure, or will circuit designers no being able to extract benefits from scaling due to power/thermal issues first?  Or will executives decide that the returns from scaling in terms of cost – due for example to design costs or limited markets supporting the volume to amortize that cost – are no longer worth it?  The panel will discuss these question in the context of both memory and logic technologies, and will further consider which of the two will end first.

• Technology Rump Sessions

  Technology Rump Sessions

  Tuesday, June 10, 8:00 pm – 10:00 pm

  R-1:    450 mm, EUV, III-V, 3D; All in 7nm? Are you serious?! 

  Organizers: C. Mazure, SOITEC and Y.-C. Yeo, National University of Singapore
  Moderator: A. Strojwas, PDF

  Panelists: 
  W. Arnold, ASML
  R. Gottscho, Lam RESEARCH
  K. Hasserjian, AMAT
  S. Iyer, IBM
  C. Maleville, SOITEC
  A. Steegen, IMEC

  The IC industry in its pursuit of technology scaling has an excellent track record of innovations and breakthroughs. In particular, the industrial ecosystem supporting IC manufacturing has had an enabling role in the making of ever denser, faster and cheaper IC products. The materials, substrate, equipment industries have introduced very successfully innovations at an incredible pace at all the levels: material, equipment, and manufacturing.

  But as the IC industry moves towards the 7nm technology node it faces the challenge of mastering simultaneously several technologies and manufacturing disruptions. The whole of the semiconductor industry is discussing moving away from the well proven Si channel, introducing III-V and/or Ge based transistors while maintaining a CMOS approach, which may request gate-all-around device architecture to control channel on/off. The stacking of wafers and chips to integrate higher level in development today may become essential to fulfill the ever increasing performance and bandwidth demands. The EUV lithography is targeted to be introduced with the 7nm technology but probably in combination with double patterning techniques. In parallel the IC makers, in order to reduce manufacturing cost, are pressuring the substrate and equipment makers to introduce a larger wafer size, shifting from the established standard of 300mm to 450mm. A simultaneous transition from decades old Silicon channel, a very mature immersion lithography and wafer size creates significant challenges for our industry.

  This panel discussion will focus on the degree of disruptions and challenges to overcome what will be necessary for this transition to occur.

   

   

• Circuits Rump Sessions

  Circuits Rump Session

  Thursday, June 12, 8:00 pm – 10:00 pm

  R-1:  Lessons and Challenges for Future Mixed-Signal, RF, and Memory Circuits

  Organizers: P. Hanumolu, University of Illinois, Urbana-Champaign, N. Lu, Etron Technology, Inc.
  Moderators: T. Lee, Stanford and N. Lu, Etron Technology, Inc.

  Panelists:
  A. Abidi, UCLA
  M. Bauer, Micron
  J.S Choi, Samsung
  C. Mangelsdorf, ADI
  A. Matsuzawa, Tokyo Institute of Technology
  U-K Moon, Oregon State University
  B. Nauta, University of Twente
  K. Zhang, Intel
  

  Designing mixed-signal circuits is prone with pitfalls. Degrading transistor performance combined with lack of poor models and fast large-scale simulators further exacerbate classical circuit problems. Is it possible to achieve 1st silicon success under this uncertainty or some of the mistakes inevitable? Experts from industry and academia will address this question and present their perspectives. They will share lessons learned in their own careers and present challenges for mixed-signal, RF and memory chips going forward. Each of the panelists will be asked to highlight the key bottlenecks in achieving 1st silicon success and outline ways to address them. The panelists will also discuss these circuits when applied to  interconnect technologies such as the 3D/2.5D integration.

  R-2:  What should circuit designers do in an era of system level design?

  Organizers: S. Dillen, Qualcomm and S. Dosho, Panasonic
  Moderators: J. Rabaey, University of California, Berkeley
  
  Panelists:
  S. Goto, Waseda University
  C-M Hung, MediaTek
  S. Naffziger, AMD
  B. Nikolic, University of California, Berkeley
  S. Ryu, Samsung
  J. Savoj, Xilinx
  E. Terzioglu, Qualcomm
  J. Warnock, IBM
  

  As technology scaling continues to follow Moore’s law, both the manufacturing cost and time to market (TTM) are becoming exorbitant.  Conversely, system-based design using licensed IP in an ASIC flow, or FPGA-based design can significantly reduce design time and thus time to market.  There are two parts to this complicated problem.  First, board-level system designers can switch to using a reconfigurable FPGA chip rather than going through the expensive, time-consuming process of developing a custom ASIC solution.  While FPGA power, performance and area (PPA) are generally worse, the increasing cost and TTM of a custom solution combined with improving FPGA PPA metrics may result in higher adoption of this solution.  Similarly, even in a custom ASIC design, foundry and foundry-partners offer many IP solutions directly to customers which can lead to a reduction in full-custom IP design, reduce risk and TTM.

  On the other hand, deep sub-micron technology challenges and designing circuits with good PPA metrics require more detailed circuit design and understanding. Also, adapting quickly to new design requirements and interface standards could require custom solutions in order to capture or maintain a market leadership position.

  Will custom VLSI design be confined to a niche market or will VLSI circuit designers still play an integral role in the design process as this design evolution continues?  A panel of VLSI circuit design experts will present their opinions on this topic and discuss what is the future of VLSI circuit design.