VLSI Techology Short Courses & Workshops

• 8:00 am | Introduction & Overview of Mobile SoC Technology Environment, G. Yeap, Qualcomm

• 8:15 am | Key Semiconductor Products, Applications and Device Drivers

  • CPU applications: Key tech/design drivers, R. Aitken, ARM
    The interaction between process technology and design for CPUs can be summarized in three questions: “How fast will a processor go?” “How much power will it consume?” and “How much area will it occupy?” Specific technology details such as device performance and SRAM Vmin can produce substantial changes in the answers to the questions, and strongly influence micro architectural development. This talk provides an overview of key metrics and their implications for CPU design.
    BIO: Robert Aitken is an ARM Fellow and heads the Silicon portion of ARM R&D. His areas of responsibility include low power design, library architecture for advanced process nodes, design/technology co-optimization, and advanced implementation techniques. His group has participated in numerous chip tape-outs, including 6 at or below the 16nm node. He holds numerous patents and has published over 70 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.
  • GPU applications: Key tech/design drivers, L. Bair, AMD
    Graphics Processing Units (GPUs) share several common technology drivers with other common digital logic products, including Central Processing Units (CPUs). However, some GPU attributes, e.g. the high degree of parallelism, drive specific technology choices, both in standalone, i.e. discrete GPU, and integrated, i.e. combined CPU and GPU, applications.
    BIO: Larry Bair is a Fellow at Advanced Micro Devices with over twenty-five years’ experience in VLSI design and process development. He obtained his S.B. and S.M. in Electrical Engineering from the Massachusetts Institute of Technology and has worked for many companies designing and manufacturing microprocessors, including Digital Equipment Corporation, Compaq, Hewlett-Packard, Intel, and, for the last nine years, AMD. Larry’s career has included transistor development, reliability characterization, analog and digital design, product debug, and the interface between chip design and fabrication. He is currently working in AMD’s Foundry Technology Organization enhancing product performance and power estimation for GPU and APU products.
  • DSP/VPE applications: Key tech/design drivers, M. Saint-Laurent, Qualcomm
    This presentation will discuss the key technology and design drivers for the DSPs and vector processing engines used in leading edge 3G/4G modems. It will give an overview of the design techniques used to deliver power, maximize energy efficiency, and control leakage. It will also discuss the process technology aspects having the most impact on these techniques.
    BIO: Martin Saint-Laurent received the B.Eng. degree (with honors) in electrical engineering from McGill University, Montréal, Canada, and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, GA, USA. From 1998 to 2005, he was with Intel Corporation, where he worked on two generations of high-frequency IA-32 processors as a custom circuit designer. His responsibilities included clock distribution and sequential element design. In 2005, he joined Qualcomm, Inc., Austin, TX, where he currently works on developing and implementing power reduction techniques for DSPs as a principal engineer.
  • FPGA applications: Key tech/design drivers, X. Wu, Xilinx
    A FPGA consists of spectrum of different circuits, such as logic and interconnect, memory, processor, IO, SERDEs and other mixed-signal blocks, It needs almost every aspects of technology – good power-performance transistors (both digital and analog) with multiple Vts, wide voltage range of IO devices, tight design rules, as well as 3D-ICs and advanced packaging technologies. We expect Si technology continual advancing while each node becomes more and more challenging. More varieties of technologies become attractive and available, and more integration such as 3D-IC, MCM, logic-memory, etc. play larger roles. Besides pushing and co-developing new technologies, Xilinx in mean time has been constantly putting effort in how to best and most efficiently utilize each technology.
    BIO: Xin Wu is responsible of silicon technology, 3D-IC and advanced package technology-design areas. He holds degrees of MSc from Peking University, China and PhD from University California, Berkeley respectively. He joined Xilinx in 1993, went through from 0.6um till now more than 12 generations of technologies, from many foundries. Currently he is working on 20nm and 16nm FPGA products.

• 10:00 am - 10:20 am | Break

• 10:20 am | System on Chip - Applications and Key Aspects

  • System on Chip – Applications and Key Aspects for RF/MS Transceiver and Connectivity, M. Zargari, Qualcomm
    Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip (SoCs). This talk describes the challenges in designing CMOS SoCs for wireless communications and in particular WiFi connectivity systems. RF transceiver architectures and building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, frequency synthesizers and baseband circuits. System-on-a-chip integration challenges such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.
    BIO: Masoud Zargari received the B.S. degree in electrical engineering from Tehran University in 1989 and M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1993 and 1997 respectively. From 1996 to 1998 he was a member of the technical staff at Wireless Access Inc., Santa Clara, CA. where he worked on the design and development of wireless systems for two-way messaging networks. In 1998 he joined Atheros Communications as a member of the founding team. He is currently a Senior Director of Engineering at Qualcomm-Atheros focusing on integrated CMOS transceivers for wireless communications. During 1999 and 2000 Dr. Zargari was a consulting assistant professor at Stanford University where he taught courses in the area of RF and analog integrated circuit design. He served on the Technical Program Committee for the IEEE International Solid-State Circuits Conference from 2009-2014.
  • System on Chip – Applications and Key Aspects for RF-Frontend, G. Yeap, Qualcomm
    The convergence of communication and computing in the form factor a smartphones and smart pads has transformed the life of everyone. The RF front-end (RFFE) that incorporates Power Amplifiers (PAs), Switches, power controller, and passives is the key enabler. Silicon solutions is penetrating into the stronghold of GaAs and pHEMT for Pas and switches. In this tutorial, We discuss the potential for silicon-based technology in providing capability for RFFE co-design and integration.
    BIO: Geoffrey Yeap is a Vice President of Engineering at Qualcomm Technologies Inc. in charge of silicon technology & foundry engineering (advanced digital CMOS, RF/analog/power-management, and bump/CPI) and foundry IP/design enablement. He has more than 20 years of semiconductor experience working at Qualcomm, Motorola and Advanced Micro Devices on microprocessor and wireless silicon technology development, new technology/product introduction and manufacturing, as well as design/technology co-optimization. Dr. Yeap earned his Ph.D. in Electrical and Computer engineering specializing in microelectronics from the University of Texas at Austin. He holds more than 50 patents and publishes more than 80 refereed journal and conference papers.

• 11:15 am | FEOL Scaling & Integration, 3rd gen FINFET Devices & Architectures, Andy Wei, Globalfoundries

  The 10nm generation will push optical lithography and the FinFET architecture to the very limits, challenging many scaling assumptions. Multiple tradeoffs will need to be made to ensure proper SoC power, performance, and cost scaling, while allowing for fast yield maturity and time to market. This shortcourse will cover scaling trends in 10nm-class SoC technologies, show the process challenges at these tight pitches, and discuss the innovations needed to ensure a healthy and scaled FEOL integration.
  Bio: Andy Wei received his B.S. in E.E. from the University of Arizona, Tucson, AZ, and his M.S. and Ph.D. in E.E. from the Massachusetts Institue of Technology, Cambridge, MA, USA, in 2000. He worked in Process Integration and Technology at AMD through 2009, taking leading-edge devices from conception to manufacturing, spanning the traditional scaling, stressor-based scaling, and high-k eras. Since 2009 he has been with GLOBALFOUNDRIES Technology Development, with focus on process scaling, architecture, and pathfinding for leading edge technologies in the FinFET era and beyond.

• 12:15 pm - 1:30 pm | Lunch

• 1:30 pm | BEOL Interconnect Scaling, Processes and Integration, T. Spooner, IBM

  As the dimensions shrink from technology node to node, the interconnect resistance and capacitance need to scale as well to minimize product performance impact. To enable this, there has been innovation in the areas of materials, processes and integration such as low-k dielectrics, conductor materials and multiple patterning. With this, there has been a need to balance the performance, reliability and manufacturability requirements. This short course is intended to provide insight to the innovation behind 10nm backend of line (BEOL) interconnect scaling.
  Bio: Terry Spooner received a Bachelor of Science in Chemistry from Rochester Institute of Technology in 1985, and was awarded a Ph.D. in Materials Engineering from Rensselaer Polytechnic Institute in 1990 for his dissertation on the measurement of excess noise in metal films. From 1990 to 1998, he was employed by Digital Equipment Corporation serving as a reliability engineer, process development engineer and technical manager at the Hudson, MA site. Terry joined International Business Machines in 1998 and has worked in the areas of unit process development, BEOL integration and technical management in East Fishkill, Yorktown Heights and most recently, Albany, NY. He has contributed to the early definition and development of several technology nodes incorporating copper and low k dielectrics for advanced bulk and high performance SOI products.

• 2:15 pm | Technology/Design Co-optimization, C. Young, TSMC

  FinFET design requires new design skills to deal with the transistor 3D structure, the quantization of device width and double patterning. This short course will start out with the advantages of FinFET transistor:

  • higher driving capability per active area, lower threshold voltage, better DIBL and Subthreshold Slope, and lower supply voltage. The short course will focus on critical issues on FinFET technology and design
  • co-optimization: standard cell layout topology and methodology, standard cell height, transistor gate length, threshold voltage, interconnect metal direction, double pattern layout. The short course also covers Place and Route methodology enhancement and CAD tool feature requirements. This short course will enable circuit designs to systematically comprehend FinFET digital circuit design.

  BIO: Charles Young joined TSMC in 2012, as Director in charge of Design and Technology Platform Leadership. He has been working on TSMC’s leading nanometer process technology, 20SoC, 16FF and beyond since. His responsibilities include process technology and design co-optimization; ensuring TSMC’s technology area-power-performance leadership. Prior to TSMC, he was with NVIDIA for more than 10 years, as Director of Hardware Engineering. He was in charges of NVIDIA Standard Cell, SRAM Compiler and custom digit circuit designs. He also established and managed NVIDIA Shanghai Research and Development Center from 2005 to 2010, serving as General Manager. He holds a BS degree in EECS from University of California, at Berkeley.

• 3:00 pm - 3:20 pm | Break

• 3:20 pm | Embedded SoC Memory: eSRAM, eNVM and eDRAM, G. Kim, Samsung

  Embedded memory has evolved during decades and plays a important role in a mobile System-On-Chip. Scaling, speed and power-consumption have been improved with the help of technology and design-architecture. eSRAM is still the main memory for CPU and GPU with most integration techniquie occupying about 30% over SoC. Then eDRAM is making the challenge to replace eSRAM for higher bandwidth and capacity. eNVM provides the key functionality of chip ID and redundancy resource in SoC. The STT-MRAM is getting attention as the new memory. This short-course covers all kinds of eMemory for applications and features in a commercial point of view. Especially, eSRAM with assist circuits and eDRAM for low-power design are in introduced.
  Bio: Gyuhong Kim received the B.S degree in electrical engineering from Yunsei University, Seoul, Korea in 1990. He joined the Semiconductor Research and Development Center, Samsung Electronics Company Ltd., Yongin, Korea, in 1990. From 1990 to 1997, he was enageged in the development Fastpage/EDO DRAM and SDR/DDR SDRAM. Since 1997, he has been working on the development of embedded memory such as embedded DRAM, embedded NVM and embedded SRAM at the System LSI Division of Samsung. Now he is a principle engineer and director of Library IP(eMemory, Standard Cell & GPIO) development team.

• 4:00 pm | Variability and DRM PDF, A. Strojwas, PDF Solutions

  This presentation will focus on the source and effects of variability in the upcoming technology nodes and on the DFM techniques aimed at combating the inherent variability to result in robust high yielding products. We will cover all key physical mechanisms for random and systematic variations in logic, embedded memory and analog/RF components of the mobile platform SOC’s. We will also demonstrate techniques for characterizing these variation sources and show results from the state-of-the-art fabrication processes. Then we will present effective DFM techniques to achieve high manufacturing yield and reliability targets without sacrificing power, performance or SOC chip area. These techniques have been implemented in the design flows of the most advanced circuits and will be illustrated by the real design examples.
  Bio: Andrzej J. Strojwas is Joseph F. and Nancy Keithley Professor of Electrical and Computer Engineering at Carnegie Mellon University. Since 1997 he has served as Chief Technologist at PDF Solutions, Inc. He has held positions at Harris Semiconductor Co., AT&T Bell Laboratories, Texas Instruments, NEC, HITACHI, SEMATECH, KLA-Tencor and PDF Solutions, Inc. He received multiple awards for the best papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Semiconductor Manufacturing and IEEE-ACM Design Automation Conference. He is also a recipient of the SRC Inventor Recognition Award. He was the Editor of the IEEE Transactions on CAD of ICAS from 1987 to 1989. He served as Technical Program Chairman of the 1988 ICCAD and Conference Chairman of the 1989 ICCAD. In 1990 he was elected IEEE Fellow.

• 4:45 pm | 2.5D or 3D Packaging for Mobile SIP, G. Van der Plas, imec

  A common feature of applications such as mobile internet, high density and 3D displays, cloud computing, gaming and high performance computing is the ever increasing need for more data and more data transfer. 3D integration technologies allow for a significant power reduction together with a strong increase in memory-logic interconnect bandwidth. This is achieved by reducing both the interconnect connection pitch and wire-length. This can be done at different levels of the electronic system hierarchy and by repartitioning the electronic system. Because of thermal limitations, some applications require the use of a so-called interposer substrate to realize high bandwidth interconnects between subsystems. This approach will also allow to take the next step in high bandwidth communication. In this presentation will review the state-of-the-art and progress in the development of 3D technology components such as TSV, micro-bumps and advanced packaging and review the benefits and challenges for 3D system design. We will report on aspects such as thermal modeling, mitigation of mechanical stress of TSV and packaging, design metrics (Keep-out-Zone), compatibility with advanced CMOS, testability and signal/power integrity to enable system designers to develop optimized 3D systems.
  Bio: Geert Van der Plas obtained the M.Sc. and Ph.D. degrees from the Katholieke Universiteit Leuven, Belgium, in 1992 and 2001, respectively. He joined imec, Belgium, in 2003, where he is a principal scientist. He has been working on energy efficient data converter, power and signal integrity and design enablement of scaled CMOS and 3D integration technologies. He has authored and co-authored over 150 papers in journals and conference proceedings and serves on the technical program committee of the symposium on VLSI circuits.

Satellite Workshop