VLSI Circuits Short Courses & Workshops

Abstract: In the last decade, energy efficiency is possibly the most pivotal design parameters in digital circuits. In this short course, we will give an overview of advances in energy efficient design. First, we will review the foundational principles of energy loss in circuits.  We will then survey the key levers that designers have available to increase efficiency, such as voltage scaling, clock gating, low swing signaling and clocking, and signal encoding. For each technique, we will discuss the design challenges that the design faces in implementing these techniques, highlighting issues such as robustness challenges, and sensitivity to PVT variations. We will conclude with a discussion of example systems from industry and academia that have implemented these techniques. 

Bio: David Blaauw received his B.S. in Physics and Computer Science from Duke University in 1986, and his Ph.D. in Computer Science from the University of Illinois, Urbana, in 1991. After his studies, he worked for Motorola, Inc. in Austin, TX, where he was the manager of the High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan where he is a Professor. He has published over 450 papers and holds 40 patents. His work has focused on VLSI design with particular emphasis on ultra low power and high performance design. He was the Technical Program Chair and General Chair for the International Symposium on Low Power Electronic and Design. He was also the Technical Program Co-Chair of the ACM/IEEE Design Automation Conference and a member of the ISSCC Technical Program Committee. He is an IEEE Fellow.

Abstract: Low power and energy efficiency are crucial to many microprocessor-based on-chip subsystems, from servers to sensors. A systems level approach is required to addressing hardware, software, and power management in order to develop modular building blocks. Ideally standard multi-voltage EDA tools and flows are supported to accelerate time-to-market rather than requiring ‘expert’ full-custom circuit design techniques. This section of the short course will cover practical case studies as well as some principles for reusable CPU-based sub-systems.

Bio: David Flynn received his B.Sc.(Hons) in Computer Science from Hatfield Polytechnic, UK and his Dr.Eng. in Electronic Engineering from the Loughborough University UK in 2007. He is a Senior Member of the IEEE and a lifetime member of the ACM. Since October 1991 he has worked for ARM Ltd, currently in the Silicon group in ARM R&D, specializing in low power design and IP deployment. Since 2008 he has also served part-time as a Visiting Professor with the University of Southampton, and is a co-director of the ARM-ECS Research Centre there. He has also served as an external technology advisory board member to ArchPro DA Inc (2004 – 2007, on acquisition by Synopsys Inc). Dr. Flynn was recognized as an ARM Fellow in 2000. He was the primary author of the Low Power Methodology Manual “LPMM” (2007). He currently serves on technical program committees for DAC and SNUG-Silicon Valley.

Abstract: Energy-efficient system design requires careful trade-offs among architecture, circuits and software level techniques. Energy consumption of a system is mainly driven by active power, standby power and duty cycle. Reducing each of these parameters helps in making the system more energy efficient. The choice of peripherals and micro-architecture of each block and system architecture to connect them together including microcontroller/DSP and memory affect the key power metrics mentioned above thus has a major impact on total energy consumption. In this short course, we will describe these trade-offs and present techniques for optimization of system energy with the help of examples.

Bio:  Srini Sridhara is a senior member of technical staff and low-power technology program manager at Texas Instruments. He received a bachelor’s degree in technology from Indian Institute of Technology, Kharagpur in 1999 and a PhD in electrical engineering from University of Illinois at Urbana-Champaign in 2006. His research interests are in ultra-low power memory design, low-power circuits, and signal processing architectures for mobile and wearable/implantable applications. He has published seventeen papers and has fifteen issued or pending patents in these areas. He serves on the technical program committees of Symposium on VLSI Circuits (VLSIC) and International Symposium on Low-Power Electronics and Design (ISLPED). He has served as a Session Chair at VLSIC (2013, 2014) and ISLPED (2010, 2012, 2013). He has been an invited speaker at several conferences including 2010 Design Automation Conference. He serves on technical advisory boards of two Semiconductor Research Corporations’ research tracks. Dr. Sridhara is a Senior Member of IEEE.

Abstract: Power delivery and power management challenges in deep sub-micron technologies, driven by increased architectural needs, low idle current targets, process scaling, and integration are expanding from generation to generation. Cost and form factor prohibit simply increasing the platform rail count to deliver the improvements. This talk will give an overview of how DC-DC converter integration, as demonstrated by the 4th Generation Intel Core Processor Family, can unlock the ability to do fine grained and fast voltage and power management. An overview of how this is achieved is presented, along with data showing how this can be of tremendous benefit satisfying the need for high performance and low idle power. Additionally, the short course will cover technical details of the implementation and highlight the system level benefits & costs.

Bio: Jonathan Douglas is a senior principal engineer at Intel corporation in Oregon. He has worked for 21 years in microprocessor design, specializing in analog circuit design and validation. Most recently his work has been in the area of power delivery integration onto leading-edge silicon. Jonathan graduated from Rensselaer Polytechnic University.

Abstract: The short course provides a design-centric treatment of ultra-low voltage logic circuits for operation at nearly minimum energy. The challenges posed by aggressive voltage scaling are discussed, and design guidelines to achieve robust/energy-efficient operation are presented. Quantitative tools are introduced to make quick estimates and design decisions at circuit level, and evaluate the impact at adjacent levels. Several academic and industrial designs are presented to gain an insight into the tradeoff between energy, performance and resiliency. Emphasis is given on design issues and solutions that significantly depart from the (often wrong) common wisdom that comes from traditional (above-threshold) designs.

Bio: Massimo Alioto received the Laurea and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001. He is currently an Associate Professor at the Electrical and Computer Engineering Department of the National University of Singapore and previously held various positions, including Associate Professor at University of Siena, Visiting Scientist at Intel Labs – CRL (2013), Visiting Professor at University of Michigan – Ann Arbor (2011-2012), BWRC – University of California, Berkeley (2009-2011), EPFL (2007). He co-authored 180+ journal/conference publications and two books. His research interests include ultra-low voltage VLSI circuits, green computing, self-powered sub-uW systems, error-aware and widely energy-scalable VLSI circuits, emerging technologies. He was IEEE Distinguished Lecturer (2010-2012) and Chair of the “VLSI Systems and Applications” Technical Committee (2011-2012). He is Associate Editor in Chief of IEEE Transactions on VLSI Systems, and served as Guest Editor of various journal special issues. He serves as Associate Editor of several journals (including ACM TODAES and IEEE TCAS-I), and he was Technical Program Chair (ICECS 2013, NEWCAS 2012, ICM 2010) and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM).

Abstract: Highly energy efficient SRAMs play an important role in many emerging ultra-low power applications. Lowering operating voltage is powerful energy consumption reduction technique for various digital designs. SRAM designers have been exploring low voltage operation despite many difficulties by introducing new memory cell topology, various kinds of assist techniques, and advanced adaptive control circuits. However, the effect of lowering operating voltage on energy reduction is relatively small compared to the logic circuits because of its architecture and low activation rate. For higher energy efficiency, design techniques with a new perspective beyond voltage scaling must be introduced. This short course will provide such a new perspective for energy efficient SRAM, as well as show an overview of wide-ranging challenges and state-of-art design techniques on energy efficient SRAM.

Bio: Shinji Miyano received the B.E. and M.E. degrees in applied physics from the University of Tokyo, Tokyo, Japan, in 1984 and 1986, respectively. In 1986, he joined Toshiba Corporation, where he developed GaAs IC, embedded DRAM, SRAM, and MEMS. From 2009 to 2013, he was serving as a manager of memory design at the Semiconductor Technology Academic Research Center. Currently he is with the Center for Semiconductor Research & Development, Semiconductor & Storage Product Company, Toshiba Corporation. His current research interests include low-power SRAM, DRAM, Analog, and system LSIs. Mr. Miyano served as a Program Committee Member for IEEE Custom Integrated Circuits Conference (CICC) from 2000 to 2003. He is a senior member of IEICE.