2002 SYMPOSIUM ON VLSI CIRCUITS 2002 VLSI Circuits Short Course "Circuit and Technology Options for Controlling Leakage" Wednesday, June 12 [Tapa III] Organizers: Stephen Kosonocky, IBM T.J. Watson Research Koichiro Ishibashi, STARC 8:30am Introduction Stephen Kosonocky, IBM T.J. Watson Research 8:45am Device Scaling, Leakage Currents, and Joint Technology and System Optimization David J. Frank, IBM T.J. Watson Research Center 9:45am Break 10:00am Overview of Gate Leakage and Prospects of a Technology Solution Akira Toriumi, University of Tokyo 11:00am Optimization and Control of VDD and Vth Tadahiro Kuroda, Keio University 12:00pm Lunch 1:30pm Multi-Vt Fully-Depleted CMOS/SOI Circuits for Low Voltage Design Koji Fujii, NTT 2:30pm Leakage Sensitive Logic and Circuits Kaushik Roy, Purdue University 3:30pm Break 3:45pm Overview of Device and Process for Low Power SRAM Jae-Hoon Jang, Samsung 4:45pm Conclusion Koichiro Ishibashi, STARC