VLSI Techology Short Courses & Workshops

Stringent requirements for contacted gate pitch size (~40nm or less) of the transistors for 5nm node strongly limit the choice of device architecture, channel and S/D materials. While gate-all-around (GAA) nano-wire or nano-sheet architectures appear to be better options for scalability than FinFETs, various technological challenges associated with the mobility degradation, parasitic capacitance and current drive competitiveness with FinFETs must be overcome. The common benefits of emerging high-mobility channel materials such as s-Si, s-SiGe, Ge and III-V may not necessarily fit in a GAA architecture due to some challenges such as ability to maintain the built-in strain in suspended structure (for s-Si or s-SiGe), low bandgap and increased parasitic bipolar effects (for Ge or III-V). Moreover, with extremely limited space remaining for the S/D in horizontal architectures, the importance of the contact resistance is much more pronounced compared to the previous generations and can set another limit to the choice of channel and S/D materials. In this lecture, we briefly review the current R&D status for various architectures as well as suitability of various material options for channel, spacer and contact considering the power management and compatibility with the choice of device architecture, for 5nm node.

About Pouya Hashemi

Pouya Hashemi received his Ph.D. degree with honors in Electrical Engineering from MIT in 2010 and is currently a research scientist at IBM T.J. Watson Research Center, NY, focusing on exploratory CMOS devices and integration of high-mobility channel materials such as strained SiGe, III-V and novel architectures for advanced CMOS generations. He has co-authored near 100 publications in peer-reviewed journals and conferences such VLSI Tech. Symposium, IEDM, EDL as well as many invited talks. As an IBM master inventor, he has over 250 pending or issued US patents. He is a Senior Member of IEEE and recipient of various recognitions and honors such as IEEE EDS George E. Smith award.

An introduction of high-mobility channel materials such as Ge and III-V semiconductors has been pursued as one of the technology boosters of MOSFETs beyond Si MOSFETs. Recently 2D materials such as MoS2 and other transition metal dichalcogenides have also joined the candidate for a channel material of extremely-scaled MOSFETs owing to their atomically thin body. The heterogeneous integration of those semiconductor on Si platform gives us further possibilities to develop new devices on the same platform. One of the significant advantages of Ge, III-V, and 2D is the band-alignment engineering. Staggered or broken band alignments among those semiconductors seem a key enabler of tunnel FETs. The bandgap tunability is another advantage for developing optoelectronic devices including lasers, modulators, and photodetectors on Si platform. Si photonics based on the heterogeneous integration enables us to integrate high-speed and low-power optical interconnection interfaces on LSI chips. In this short course, the recent progresses of process and device technologies of Ge, III-V, and 2D for More Moore, Beyond CMOS, as well as More than Moore will be reviewed.

About Mitsuru Takenaka

Mitsuru Takenaka received his B.E., M.E., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 1998, 2000, and 2003, respectively. During 2003-2007, he was a research fellow of the Optoelectronics Industry and Technology Development Association, where he was engaged in research on photonic routers. In 2007, he joined the Department of Electrical Engineering, the University of Tokyo, as a lecturer. In 2008, he became an associate professor at the Department of Electrical Engineering and Information Systems, the University of Tokyo, where he currently works. His research interests presently focus on heterogeneous integration of Ge, III-V compound semiconductors, and 2D materials on Si platform for electronic-photonic integrated circuits. He has authored and co-authored more than 500 papers in technical journals and international conferences for photonics and electronics. He has also served as technical program committee and steering committee members of highly-reputed international conferences including International Electron Device Meeting (IEDM), Device Research Conference (DRC), International Conference on Indium Phosphide and Related Materials (IPRM), and International Conference on Solid State Device and Materials (SSDM). He received the Young Scientist Award for the Presentation of an Excellent Paper in 2003 from the JSAP, the Young Researchers’ Award in 2005 from the IEICE, IEEE EDS Paul Rappaport Award in 2014. Dr. Takenaka is a member of IEEE Photonics Society, IEEE Electron Devices Society, the Institute of Electronics, Information, and Communication Engineers (IEICE), and the Japan Society of Applied Physics (JSAP).

The presentation will describe various PPA and yield challenges encountered while scaling to the latest cutting edge tech nodes and various considerations to mitigate such challenges. We feel many of these challenges and trade-offs are applicable to 5nm designs and will need to be considered carefully.

About Paul Penzes

Paul Penzes is a Senior Director of Engineering at Qualcomm Technologies Inc. He leads the Design Technology (DTECH) team within the Central Engineering and Technology organization. He manages design technology integration, digital testchips, timing methodology and sign-off, and performance-power-area (PPA) R&D. Prior to Qualcomm, Paul was an Associate Technical Director and Distinguished Engineer at Broadcom Inc. Paul has +25 patents issued, +15 pending, and has a B.S., an M.S. and a Ph.D in Computer Science from the California Institute of Technology, Pasadena.

As VLSI technology progresses to the sub-10nm nodes, interconnect RC and power dissipation scaling play an increasingly complex – and increasingly important – role in overall product performance. Though the transistor itself (i.e. FEOL) has traditionally been the rate-limiting step, inefficiencies in data storage and movement (i.e. the MOL and BEOL interconnect system) now dominate many aspects of holistic computing performance. This short course will present an historical overview of interconnect materials and process integration changes introduced across multiple technology nodes in order to meet evolving product needs. And because several aspects of interconnect no longer scale well to the 5nm node (or because they must simultaneously satisfy opposing requirements), current and future tradeoffs in interconnect architecture (e.g. new conductors, heterogeneous integration, photonics) will also be discussed in light of their impact upon power, performance, area, cost, and reliability.

About Robert Fox

Robert Fox is the Director of BEOL (Back-End-Of-Line) Technology and Process Integration in the Advanced Technology Development organization in GLOBALFOUNDRIES. He has over 20 years of global experience in BEOL Process Integration, having lived and worked in France, Singapore, Germany, and the United States. Prior to joining GLOBALFOUNDRIES, he held positions of increasing responsibility in Freescale Semiconductor, Motorola’s Advanced Products Research and Development Laboratory, and International SEMATECH. His experience with interconnect characterization spans 3-inch to 300-millimeter wafers, Al to W to Cu metallization, hard to soft to no (e.g. airgap) dielectrics, and critical dimensions from microns to nanometers. He is the author or coauthor of more than 30 papers and patents related to BEOL materials and process integration.

The 3D integration technology using TSV has significantly progressed for these years as represented by 3D-stacked DRAM such as HMC and HBM. These 3D-stacked DRAMs have extremely high data bandwidth of 128GB/s to 256GB/s. The 3D-stacked structure is also employed in a CMOS image sensor (CIS). A back-illuminated stacked CIS with two layers has been already in a volume production. In addition to these 3D-stacked DRAM and 3D-stacked image sensor, heterogeneous 3D/2.5D integration technology has recently attracted much attention since it is indispensable for future IoT and AI. In a heterogeneous integration technology, different kinds of chips such as compound semiconductor device chip, photonic device chip, spintronic device chip and MEMs will be stacked on CMOS chips or interposer substrates. IoT is expected to offer advanced connectivity of devices, systems, and services including machine-to-machine communications and human-to-machine communications for AI. Low power consumption, small form factor and multi-functionality are required for embedded devices in IoT. Heterogeneous 3D/2.5D integration can provide these embedded devices with low power consumption, small form factor and multi-functionality. In this lecture, such heterogeneous 3D/2.5D integration technology for IoT and AI including monolithic 3D integration technology is described.

About Mitsumasa Koyanagi

Mitsumasa Koyanagi received Ph.D. degree in electronic engineering from Tohoku University, Sendai, Japan, in 1974. He joined the Central Research Laboratory, Hitachi Ltd. in 1974 where he worked on research and development of MOS memory device and process technology and invented a stacked capacitor DRAM cell which is the first commercialized 3D device. In 1985, he joined the Xerox Palo Alto Research Center, California where he worked on research and development of sub-micron CMOS devices, poly-Si TFTs and the design of analog/digital LSIs. In 1988 he joined Hiroshima University as a professor where he worked on sub-0.1um device technology, device modeling, poly-Si TFTs, 3-D integration technology, optical interconnection and parallel computer system specific for scientific computation. Since 1994, he has been a professor in Tohoku University where his current interests are 3-D integration technology, optical interconnection, nano-CMOS devices, memory devices, parallel computer system, retinal prosthesis chip, brain-machine interface (BMI) devices and neuromorphic chip. He established the 3D LSI fabrication facility for 12-inch wafers, GINTI (Global Integration Initiative) in 2013 and became a director. He was awarded IEEE Jun-ichi Nishizawa Medal in 2006, IEEE Cledo Brunetti Award in 1996, JSAP Outstanding Achievement Award in 2015, Japanese Government Medal of Honor with Purple Ribbon in 2011, Award of Ministry of Education, Culture, Sports, Science and Technology in 2001, JSAP Optoelectronic Technology Achievement Award in 2004, SSDM Award in 1994, Okouchi Memorial Technology Prize in 1990, and 3DIC Pioneer Award (3D-ASIP) in 2015. He is an IEEE life fellow and a JSAP fellow.

The analog/RF circuits in 16nm beyond FinFET technology outperform the circuits in 16nm due to improvements on device/process, interconnect, and layout design flow. On device/process side, new improvements are: ~7dB lower flicker noise device,1-order lower leakage MOS capacitor. On the advanced interconnect process, new improvements are: higher capacitance density metal-over-metal capacitor, different pitches and better metal EM at high temperature. On layout design flow, new improvements are: coloring flow and layout dependent heat-sink flow. These device performance improvements make the analog/RF circuit design friendly in the scaled technology.

This talk will cover 16nm beyond technology improvement on device components (MOS, R. L, MoM cap, varactor, BJT) and their implementation in analog/RF circuits, FinFET self-heating solution in output driver to maintain stable circuit performance, and some layout guidelines to mitigate process variation.

About Fu-Lung Hsueh

Fu-Lung Hsueh is a TSMC Academy Fellow, and Director of Mixed-signal and RF Solution Division, R&D. He joined TSMC in September 2003. He received PhD in electrical engineering, Lehigh University, in 1982, and had worked at RCA David Sarnoff Research Center, Princeton, NJ, since 1981 for 22 years. He has 93 patents issued and over 78 papers published. Specialized Professional Competence: VLSI circuit designs in high-speed ADCs, PLL, DAC, RF, CMOS imaging sensors, CCD visible/UV imagers, High density active-matrix electroluminescent display (AMEL) in silicon-on-insulator (SOI), Infrared PtSi Focal Plane Array imagers, Single-event upset (SEU) immune and state-retention memories. He received 5 Technical Achievement Awards in 2002, 1997, 1994, 1992, 1989, respectively, at Sarnoff Corporation. In 2007 and 2008, he received three TSMC Chairman Innovation Awards. He received two best paper awards from SOI and SID Conferences in 1994. He was an ISSCC TPC member in Technology Direction from 2011-2015, served as Session Chair, co-Chair, and Tutorial and Forum coordinators. He gave a Short course at 2012 Symposium on VLSI Circuits, and was a panelist of evening Rump session in 2013. He was a TPC member of A-SSCC during 2008-2011.

SRAM and Flash memories are the basis of embedded memory subsystems used in microcontroller applications. Design of embedded memories allows for product optimization and differentiation through careful consideration of factors such as the application, performance, power, safety, and security. This talk will explore how these factors shape considerations for the design implementation of SRAM and flash memory solutions embedded into microcontrollers. We will examine the different thought processes behind embedded memory design driven by IOT applications where power/performance can be key differentiators and Automotive applications where Zero Defects and Functional Safety (ISO26262) are simply expected. Some considerations such as security are becoming universal expectations for IOT and Automotive applications.

About Thomas Jew

Thomas Jew has worked on embedded SRAM, Flash, and MRAM designs integrated in microcontrollers for IOT and automotive applications. He is a Technical Director in NXP’s Global Technology Innovation team and currently leads the Automotive Non-Volatile Memory Design Group developing Zero Defect, Non-Volatile Memory solutions embedded in Advanced Safety-Aware and Secure Microcontrollers used to power automobiles. Prior to joining NXP by way of Freescale Semiconductor/Morotola, he worked for Texas Instruments, designing discrete flash memories. Thomas holds multiple patents and received his BS and MS degrees in Electrical Engineering from Texas A&M University in 1988 and 1991 respectively.

The lecture will cover the challenges of designing a processor inside a DRAM die, including

• DRAM process specificities affecting the design of a CPU
• Micro-architecture selection
• Interleaved pipeline advantages and disadvantages
• Motivation for an uncompatible instruction set
• PSRAM usages and limitations
• Analog team and CPU team cooperation
• Manufacturing test strategies
• On die PIM economics considerations

About Fabrice Devaux

• Master of Advanced Studies in micro-electronics at PARIS 6 university (1992) 10 years as CPU designer, then architect, in various companies: startup (A.C.R.I), design service (SOREP), large (ST micro)
• Founded in 2003 TRANGO-virtual processor, an embedded processor virtualization company, bought by VMWARE in 2008.
• Start working on in memory processing in 2011, working full time on the subject since 2012.
• Co-Founder and CTO of uPmem (incorporated in 2015).
• uPmem conceives a Processor In Memory, referred to as DPU (Dram Processing Unit), integrable into a DRAM die.