PLENARY, PANELS and LUNCHEON

Tuesday, June 19

Scott J. DeBoer

Executive Vice President, Technology Development
Micron Technology, Inc.

Scott DeBoer leads Micron’s global technology development efforts related to the scaling of current memory technologies (DRAM, NAND and NOR), as well as the investigation of new memory technology solutions, packaging and mask technology to support Micron’s future requirements.

Dr. DeBoer joined Micron in 1995 and has served in a variety of technical and managerial positions leading up to his appointment as Vice President of Process R&D in 2007. He currently serves on the boards of IM Flash Technologies, MP Mask LLC, EUV LLC, and the governing council of STARnet Research Initiative.

Dr. DeBoer completed his undergraduate degree at Hastings College in Hastings, Nebraska. He earned a master’s degree in physics and a doctorate in electrical engineering from Iowa State University.

Satoru Miyano

Human Genome Center, Institute of Medical Science
University of Tokyo

Satoru Miyano, PhD, is the Director of Human Genome Center, Institute of Medical Science, University of Tokyo. He received the B.S. (1977), M.S. (1979) and PhD (1984), all in Mathematics from Kyushu University, Japan. He has been working in the field of Bioinformatics and joined Human Genome Center as a professor in 1996. His research mission is to develop “Computational Medical Systems Biology towards Genomic Personalized Medicine”, in particular, cancer research and clinical sequence informatics. He has been involved as PI with MEXT Scientific Research on Innovative Areas “Systems Cancer Project”, “Systems Cancer in Neodimension”, the International Cancer Genome Consortium, MEXT Large-Scale Data Analysis with K computer, and Post-K Computer Project. He is a 2013 Fellow of  the International Society for Computational Biology. 1994 IBM Science Award (Computer Science), 2016 Uehara Award for cancer genomics.

Tuesday, June 19

Abstract: The current resurgence of artificial intelligence is due to advances in deep learning. Systems based on deep learning now exceed human capability in speech recognition, object classification, and playing games like Go. Deep learning is enabled by powerful, efficient computing hardware. The algorithms used have been around since the 1980s, but it has only been in the last few years – when powerful GPUs became available to train networks – that the technology has become practical. This talk will review the current state of deep learning, describe recent research on deep learning hardware, and explain how these systems are leading to more capable AI.

Dr. Bill Dally

Chief Scientist, Senior Vice President, Nvidia

Dr. Bill Dally is Chief Scientist and Senior Vice President of Research at NVIDIA Corporation and a Professor (Research) and former chair of Computer Science at Stanford University. Dr. Dally and his group have developed system architecture, network architecture, signaling, routing, and synchronization technology that can be found in most large parallel computers today. While at Bell Labs Bill contributed to the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. At the Massachusetts Institute of Technology his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms.  At Stanford University his group has developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations, the Merrimac supercomputer, which led to GPU computing, and the ELM low-power processor.  Bill is a Member of the National Academy of Engineering, a Fellow of the IEEE, a Fellow of the ACM, and a Fellow of the American Academy of Arts and Sciences.  He has received the ACM Eckert-Mauchly Award, the IEEE Seymour Cray Award, the ACM Maurice Wilkes award, and the IPSJ FUNAI Achievement Award.  He currently leads projects on computer architecture, network architecture, circuit design, and programming systems. He has published over 200 papers in these areas, holds over 100 issued patents, and is an author of the textbooks, Digital Design: A Systems Approach, Digital Systems Engineering, and Principles and Practices of Interconnection Networks.

Abstract: Since its founding in 1962, SECOM has been striving to create a plentiful and comfortable society through services with advanced technology. Our corporate philosophy is to contribute to human well-being, and our achievements are highly praised by society. Our wide variety of services contributes to realizing high social satisfaction for each and every person by cooperating with public services and other company services. VLSI technology has contributed to the realization of our service. That is because VLSI technology is a fundamental technology indispensable in all areas of society. On the other hand, its value is realized to the general public only after being implemented into advanced and sophisticated services. In other words, it is very important to attack societal problems from both the technology and services sides. With great respect for VLSI technology, we will continue to strive to create useful services for society. This spirit is embodied in our 2030 vision, the “ANSHIN platform”. The “ANSHIN platform” is a service platform anchored in the relationship of trust that SECOM has cultivated with society. Created in collaboration with partners who share SECOM’s philosophy, this platform is designed to provide peace of mind to people in their everyday lives, as well as to society as a whole. Innovation by SECOM and in VLSI technology continues to generate new services to society; and their integration will help us realize a plentiful society through the “ANSHIN platform”.

Mr. Tsuneo Komatsuzaki

Adviser, SECOM

Mr. Tsuneo Komatsuzaki received his B.A. in Science and Engineering from Waseda University, Tokyo, Japan, in 1978. After joining SECOM, as a corporate staff of founder, he has held diverse positions such as a local general manager, a director of technical and marketing sections. In addition, he has been in charge of planning and promoting new businesses such as medical services, disaster prevention and geography information. He was appointed as an Executive Officer in 2005, a Director of Intelligent Systems Laboratory in 2009, a Managing Executive Officer in 2014. He is currently an adviser to the CEO. His activities outside SECOM are also various, most of them are related to the government and academia.

Monday, June 18, 8:00pm

Is the CPU dying or dead? Are accelerators the future of computation?

Moderator: Rob Aitken, ARM

Panelists:

• Bill Dally (nVidia)
• Denis Dutoit (CEA-Leti)
• Sailesh Kottapalli (Intel)
• Joe Macri (AMD)
• Martin Fink (Western Digital)
• Masato Motomura (Hokkaido Univ.)
• Yujun Li (TSMC)
• Hiroshi Nakamura (Univ. of Tokyo)

Abstract: As Moore’s law slows down and processor architecture innovations move away from single thread performance, the future of compute seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel looks at future computing workloads and innovative technology and circuit solutions that enable them, from moving computation closer to memory to bio-inspired systems.

Tuesday, June 19
8:00 p.m. – 10:00 p.m.

Storage Class Memories: Who cares? DRAM is Scaling Fine, NAND is Stacking Great

Moderator: Prof. Bruce Jacob (University of Maryland)

Panelists: All confirmed

• Greg Atwood, Senior Fellow (Micron)
• Al Fazio, Senior Fellow (Intel)
• Martin Fink, CTO (WD)
• Dae Seok Byeon, Master (Samsung)
• Kazumi Ino, Technology Executive (Toshiba Memory)
• Gary Tressler, Distinguished Engineer (IBM)

Abstract: Memory – DRAM and NAND scaling, though difficult, has continued to persist due to rapid innovations and continued engineering. While new challenges both economic and fundamental pose challenges to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question is- who really cares now? System architects, DRAM/NAND manufacturers? End users? In this panel discussion, we will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

Tuesday, June 19, 8:00pm

What’s the next big thing after smartphones?

Moderator: Tom Lee (Stanford)

Panelists:

• Christopher Patrick (Qualcomm)
• Ewout Martens (imec)
• John Suh (Hyundai)
• John Wei (TSMC)
• Shoajun Wei (Tsinghua)
• Vivek De (Intel)
• Meng-Fan Cheng (NTHU)
• Hirotaka Hara (Renesas)

Abstract: Smartphones have driven the industry for more than a decade, but the pace of innovation is slowing and market saturation is occurring. What will be the next big thing? The internet of things? Automotive electronics? Virtual reality? Something else? We have assembled a set of panelists with diverse expertise to discuss the possibilities.

Abstract: Contemporary computers are formed of a few billion transistors, running at gigahertz clock rates and consuming several hundred watts of power; the human brain is formed of 100 billion neurons, running at 20 Hz and consuming 20 watts of power. Each form factors has its advantages: a computer can process enormous piles of data tirelessly and far more rapidly than any human; even an infant brain can make inferences about the world that no computer can even approaches. There is reason to believe that the mind is computable, and so we are driven to find ways to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. In this presentation, we’ll examine the journey of inventing the hardware of the mind, from the Iliad to da Vinci to Edison to Turing to today. Along the way, we’ll examine how our growing understanding of the brain is informing the engineering of silicon, and we’ll explore how the laws of physics and the laws of humanity constrain our journey.

Grady Booch

IBM

Grady Booch is Chief Scientist for Software Engineering at IBM Research where he leads IBM’s research and development for embodied cognition. Having originated the term and the practice of object-oriented design, he is best known for his work in advancing the fields of software engineering and software architecture. A co-author of the Unified Modeling Language (UML), a founding member of the Agile Alliance, and a founding member of the Hillside Group, Grady has published six books and several hundred technical articles, including an ongoing column for IEEE Software. Grady is also a trustee for the Computer History Museum. He is an IBM Fellow, an ACM and IEEE Fellow, has been awarded the Lovelace Medal and has given the Turing Lecture for the BCS, and was recently named an IEEE Computer Pioneer. He is currently developing a major trans-media documentary for public broadcast on the intersection of computing and the human experience.