Welcome to the 2005 Symposium on VLSI Technology
On behalf of the Organizing Committee, it is our great pleasure to
invite you to the 2005 Symposium on VLSI Technology which will
be held from June 14-16 in Kyoto, Japan.
This symposium started in 1981 as an international forum on the
latest research and developments in the field of VLSI technologies
and their applications, and has since then established its position as a
premiere conference for the field. We will be celebrating the 25th
anniversary of the symposium this year. For this commemorative
occasion, the Program Committee consisting of more than 40
members worldwide has selected 90 top quality papers from a record
high of 255 submitted papers, and has organized 22 technical
sessions for the Kyoto symposium. We are also delighted to have
two very distinguished invited speakers for the plenary session. Dr.
Fujio Nakajima of Panasonic AVC Networks Company, Matsushita
Electric, will present a talk on “Innovation in Digital Home
Appliances and the Role of Semiconductors” and Dr. Gilbert J.
Declerck will give a talk on “A Look into the Future of
Nanoelectronics”.
Three Rump Sessions are planned for the evening of June 15 as a
means to facilitate informal discussion among attendees. Two of the
Rump Sessions are regular sessions covering specific technologyrelated
topics of timely interest:
1. Metal Gate: How, When and If?
2. Will Planar CMOS End? When? Why?
The third is a joint Session with the Symposium on VLSI Circuits. It
will focus on fluctuation with the title “Variability Has Stopped
Scaling: Who Will Conquer the Issues of Variability?”
A one-day Short Course, scheduled for Monday June 13, will cover
“Technologies for 45nm/32nm Nodes”. This should be an excellent
opportunity for experienced as well as new engineers to broaden
their technical base.
The symposium registration fee covers all of the sessions including
the Rump Sessions, the conference digest, the conference banquet,
and a DVD containing all of the contents of the Digests from the
past 25 years as a commemorative gift. Registration for the Short
Course includes the attendance of the short course as well as a
booklet containing the short course presentation materials. The
detailed registration fees and hotel reservation schedules are
included in the Advance Program.
We look forward to seeing you at this very exciting symposium in
beautiful Kyoto and we are sure that you will find the conference
exciting and rewarding.
|
Shin'ichiro Kimura |
Jason Woo |
| Program Chair |
Program Co-Chair |
CONFERENCE SCHEDULE
Sunday, June 12 |
8:00-17:00 |
Registration |
| Monday, June 13 |
7:00 |
Breakfast |
| 8:00 |
Registration |
| 8:55-12:15 |
Short Course [Shunju] |
| 13:45-17:00 |
Short Course [Shunju] |
| 18:00-20:00 |
Reception [Suzaku] |
| Tuesday, June 14 |
7:00 |
Breakfast |
| 8:00 |
Registration |
8:25-10:15 |
Session 1 |
Welcome and Plenary Session [Shunju] |
| 10:30-12:10 |
Session 2 |
Highlights [Shunju] |
| 13:30-15:10 |
Session 3A |
Strain Enhanced CMOS I [Shunju] |
| Session 3B |
DRAM [Suzaku] |
| 15:25-17:30 |
Session 4A |
Metal Gate Technology [Shunju] |
| Session 4B |
Analog / RF Devices [Suzaku] |
| 19:00-21:00 |
Dinner [Shunju] |
| Wednesday, June 15 |
7:00 |
Breakfast |
| 8:30-10:10 |
Session 5A |
FUSI Metal Gate Technology [Shunju I] |
| Session 5B |
(110) and Ge Channel Transistors [Shunju II] |
| 10:30-12:10 |
Session 6A |
Gate Dielectric Reliability I [Shunju I] |
| Session 6B |
Advanced Memories I [Shunju II] |
| 13:30-15:10 |
Session 7A |
Multi-Gate Fin FET Technology [Shunju I] |
| Session 7B |
Flash Memory I [Shunju II] |
| 15:25-17:30 |
Session 8A |
Advanced CMOS Technology I [Shunju I] |
| Session 8B |
Process Technology [Shunju II] |
| 20:00-22:00 |
Rump Sessions [Suzaku, Shunju] |
| Thursday, June 16 |
7:00 |
Breakfast |
| 8:30-10:10 |
Session 9A |
Novel Device Concepts [Shunju I] |
| Session 9B |
Gate Dielectric Reliability II [Shunju II] |
| 10:30-12:10 |
Session 10A |
Strain Enhanced CMOS II [Shunju I] |
| Session 10B |
Advanced Memories II [Shunju II] |
| 13:30-15:10 |
Session 11A |
Advanced Fin FET Technology [Shunju I] |
| Session 11B |
Flash Memory II [Shunju II] |
| 15:25-17:30 |
Session 12A |
Advanced CMOS Technolgoy II [Shunju I] |
| Session 12B |
High k Dielectric Technology [Shunju II] |
PROGRAM
Session 1 |
Welcome and Plenary Session [Shunju] |
| Chairpersons |
S. Kimura, Hitachi Ltd.
J. Woo, University of California, Los Angeles |
8:25 |
1-1 |
Welcome and Opening Remarks |
| |
K. Maeguchi, SIRIJ
B. Havemann, Novellus Systems |
8:40 |
1-2 |
25th Anniversary Speech |
|
|
T. Sugano, Toyo University, Japan Science and Technology Corporation
R. Jaeger, Auburn University |
8:55 |
1-3 |
Innovation in Digital AV Products and the Role of Semiconductors (Invited) |
| |
F. Nakajima, Matsushita Electric Industrial Co., Ltd. |
9:35 |
1-4 |
A Look Into the Future of Nanoelectronics (Invited) |
| |
G. Declerck, IMEC |
Session 2 |
Highlights [Shunju] |
| Chairpersons |
S.S. Chung, National Chiao Tung Univ.
M.-R. Lin, AMD |
10:30 |
2-1 |
Dual Stress Liner Enhancement in Hybrid Orientation Technology |
|
Abstract
|
C.D. Sheraw, M. Yang**, D.M. Fried, G. Costrini**,
T. Kanarsky**, W.-H. Lee, V. Chan, M.V. Fischetti,
J. Holt, L. Black*, M. Naeem, S. Panda, L. Economikos, J. Groschopf*, A. Kapur, Y. Li, R. T. Mo, A. Bonnoit, D. Degraw, S. Luning*, D. Chidambarrao, X. Wang, A. Bryant, D. Brown, C.-Y. Sung**, P. Agnello,
M. Ieong**, S.-F. Huang, X. Chen and M. Khare |
| IBM Systems & Technology Group, *IBM Semiconductor Research and Development Center (SRDC) and **IBM T. J. Watson Research Center, USA |
10:55 |
2-2 |
High Density and Fully Compatible Embedded DRAM Cell with 45nm CMOS Technology (CMOS6) |
|
Abstract
|
T. Sanuki, Y. Sogo*, A. Oishi, Y. Okayama, R. Hasumi, Y. Morimasa, T. Kinoshita, T. Komoda, H. Tanaka,
K. Hiyama, T. Komoguchi*, T. Matsumoto*, K. Oota*, T. Yokoyama*, K. Fukasaku*, R. Katsumata, M. Kido, M. Tamura, Y. Takegawa, H. Yoshimura, K. Kasai,
K. Ohno*, M. Saito*, H. Aochi, M. Iwai, N. Nagashima*, F. Matsuoka, Y. Okamoto* and T. Noguchi |
| Toshiba Corporation and *Sony Corporation, Japan |
11:20 |
2-3 |
Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183µm2 6T-SRAM Cell by Immersion Lithography |
|
Abstract
|
H.-Y. Chen, C.-Y. Chang, C.-C. Huang, T.-X. Chung, S.-D. Liu, J.-R. Hwang, Y.-H. Liu, Y.-J. Chou, H.-J. Wu, K.-C. Shu, C.-K. Huang, J.-W. You, J.-J. Shin, C.-K. Chen, C.-H. Lin, J.-W. Hsu, B.-C. Perng, P.-Y. Tsai, C.-C. Chen, J.-H. Shieh, H.-J. Tao, S.-C. Chen, T.-S. Gau and
F.-L. Yang |
| Taiwan Semiconductor Manufacturing Company, Taiwan, ROC |
11:45 |
2-4 |
Feasibility Study of a Novel Molecular-Pore-Stacking (MPS), SiOCH Film in Fully-scale-down, 45nm-node Cu Damascene Interconnects |
|
Abstract
|
M. Tada, H. Ohtake, M. Narihiro, F. Ito, T. Taiji*,
M. Tohara*, K. Motoyama*, Y. Kasama*, M. Tagami, M. Abe, T. Takeuchi, K. Arai, S. Saito, N. Furutake,
T. Onodera, J. Kawahara**, K. Kinoshita**, N. Hata***, T. Kikkawa***, ****, Y. Tsuchiya*, K. Fujii*, N. Oda*, M. Sekine* and Y. Hayashi |
| NEC Corporation, *NEC Electronics, **MIRAI-ASET, ***MIRAI-ASRC AIST and ****Hiroshima University, Japan |
Session 3A |
Strain Enhanced CMOS I [Shunju] |
| Chairpersons |
H. Wakabayashi, NEC Corp.
M. Ieong, IBM Microelectronics |
13:30 |
3A-1 |
Layout Impact on the Performance of a Locally Strained PMOSFET |
|
Abstract
|
G. Eneman*,**, P. Verheyen, R. Rooyackers, F. Nouri***, L. Washington***, R. Degraeve, B. Kaczer,
V. Moroz****, A. De Keersgieter, R. Schreutelkamp***, M. Kawaguchi***, Y. Kim***, A. Samoilov***,
L. Smith****, P. P. Absil, K. DeMeyer*, M. Jurczak and S. Biesemans |
| IMEC, *ESAT-INSYS, **The Fund for Scientific Research, Belgium, ***Applied Materials and ****Synopsys, USA |
13:55 |
3A-2 |
Dramatically Enhanced Performance of Recessed SiGe Source-Drain PMOS by In-Situ Etch and Regrowth Technique (InSERT) |
|
Abstract
|
T. Ueno, H.S. Rhee, S.H. Lee, H. Lee, D.S. Shin,
Y.-S. Jin, S. Maeda and N.-I. Lee |
| Samsung Electronics Co., Ltd., Korea |
14:20 |
3A-3 |
Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement |
|
Abstract
|
D. Zhang, B.Y. Nguyen, T. White, B. Goolsby, T. Nguyen, V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, Y. Shiho, A. Thean, D. Theodore, M. Canonico, S. Zollner, S. Bagchi, S. Murphy, R. Rai, J. Jiang, M. Jahanbani, R. Noble, M. Zavala, R. Cotton, D. Eades, S. Parsons, P. Montgomery, A. Martinez, B. Winstead, M. Mendicino, J. Cheek,
J. Liu, P. Grudowski, N. Ranami, P. Tomasini.*, C. Arena*, C. Werkhoven*, H. Kirby*, C.H. Chang**, C.T. Lin**, H.C. Tuan**, Y.C. See**, S. Venkatesan, V. Kolagunta, N. Cave and J. Mogab |
| Freescale Semiconductor Inc., *ASM, USA and **Taiwan Semiconductor Manufacturing Company, Taiwan |
14:45 |
3A-4 |
Investigation of CMOS Devices with Embedded SiGe Source/Drain on Hybrid Orientation Substrates |
|
Abstract
|
Q. Ouyang, M. Yang, J. Holt*, S. Panda*, H. Chen*, H. Utomo*, M. Fischetti, N. Rovedo*, J. Li*, N. Klymko*, H. Wildman*, T. Kanarsky*, G. Costrini*, D.M. Fried*, A. Bryant*, J.A. Ott, M. Ieong and C.-Y. Sung |
| IBM T. J Watson Research Center and *IBM Systems and Technology Group, USA |
Session 3B |
DRAM [Suzaku] |
| Chairpersons |
J. T. Moon, Samsung Electronics Co., Ltd.
L.C. Tran, Micron |
13:30 |
3B-1 |
Vertex Channel Array Transistor (VCAT) Featuring Sub-60nm High Performance and Highly Manufacturable Trench Capacitor DRAM |
|
Abstract
|
M. Kito, R. Katsumata, M. Kondo, S. Ito, K. Miyano, M. Kido, H. Yasutake, Y. Nagata*, N. Aoki, H. Aochi and A. Nitayama |
| Toshiba Corporation and *Toshiba Information Systems Corporation, Japan |
13:55 |
3B-2 |
S-RCAT (Sphere-Shaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM Feature Size and Beyond |
|
Abstract
|
J.Y. Kim, H.J. Oh, D.S. Woo, Y.S. Lee, D.H. Kim, S.E. Kim, G.W. Ha, H.J. Kim, N.J. Kang, J.M. Park, Y.S. Hwang, D.I. Kim, B.J. Park, M. Huh, B.H. Lee, S.B. Kim, M.H. Cho, M.Y. Jung, Y.I. Kim, C. Jin, D.W. Shin, M.S. Shim, C.S. Lee, W.S. Lee, J.C. Park, G.Y. Jin, Y.J. Park and K. Kim |
| Samsung Electronics Co., Korea |
14:20 |
3B-3 |
A 6F2 DRAM Technology in 60nm Era for Gigabit Densities |
|
Abstract
|
C. Cho, S. Song, S. Kim, S. Jang, S. Lee, H. Kim,
Y. Sung, S. Jeon, G. Yeo, Y. Kim, Y. Kim, G. Jin and K. Kim |
| Samsung Electronics Co., Korea |
14:45 |
3B-4 |
Scaled 1T-Bulk Devices Built With CMOS 90nm Technology for Low-Cost eDRAM Applications |
|
Abstract
|
R. Ranica, A. Villaret, P. Malinge, G. Gasiot, P. Mazoyer, P. Roche, P. Candelier, F. Jacquet, P. Masson*,
R. Bouchakour*, R. Fournel, J.P. Schoellkopf and
T. Skotnicki |
| STMicroelectronics and *L2MP UMR-CNRS, France |
Session 4A |
Metal Gate Technology [Shunju] |
| Chairpersons |
K. Shibahara, Hiroshima University
D. Gravesteijn, Philips Research Leuven |
15:25 |
4A-1 |
Lanthanide-Incorporated Metal Nitrides with Tunable Work Function and Good Thermal Stability for NMOS Devices |
|
Abstract
|
C. Ren*, D.S.H. Chan*, Faizhal B. B.*, M.-F. Li*,**, Y.-C. Yeo*, A.D. Trigg**, A. Agarwal**,
N. Balasubramanian**, J.S. Pan***, P.C. Lim*** and D.-L. Kwong**,**** |
| *National University of Singapore, **Institute of Microelectronics (IME), ***Institute of Materials Research and Engineering (IMRE), Singapore and ****University of Texas, USA |
15:50 |
4A-2 |
HfO2/Metal Stacks: Determination of Energy Level Diagram, Work Functions and Their Dependence on Metal Deposition |
|
Abstract
|
S. Zafar, V. Narayanan, A. Callegari, F.R. McFeely,
P. Jamison, E. Gusev, C. Cabral and R. Jammy |
| IBM Semiconductor Research & Development Center (SRDC) and IBM, T.J. Watson Research Center, USA |
16:15 |
4A-3 |
Systematic Investigation of Amorphous Transition-Metal-Silicon-Nitride Electrodes for Metal Gate CMOS Applications |
|
Abstract
|
H.C. Wen******, H.N. Alshareef*, H. Luan**, K. Choi, P. Lysaght, H.R. Harris***, C. Huffman*, G.A. Brown, G. Bersuker, P. Zeitzoff, H. Huff, P. Majhi**** and B.H. Lee***** |
| Sematech, *Texas Instruments, **Infineon, ***AMD, ****Intel, *****IBM assignee and ******University of Texas, USA |
16:40 |
4A-4 |
Dual Metal Gate Process by Metal Substitution of Dopant-Free Polysilicon on High-K Dielectric |
|
Abstract
|
C.S. Park, B.J. Cho, W.S. Hwang, W.Y. Loh*, L.J. Tang* and D.-L. Kwong* |
| National University of Singapore and * Institute of Microelectronics, Singapore |
17:05 |
4A-5 |
Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric |
|
Abstract
|
Z.B. Zhang*, S.C. Song, C. Huffman*, J. Barnett,
N. Moumen**, H. Alshareef*, P. Majhi***, M. Hussain, M.S. Akbar, J.H. Sim, S.H. Bae, B. Sassman and
B.H. Lee** |
| SEMATECH, *Texas Instruments Assignee, **IBM Assignee and ***Intel Assignee, USA |
Session 4B |
Analog / RF Devices [Suzaku] |
| Chairpersons |
T. Dan, Sanyo Electric Co., Ltd.
C. Bulucea, National Semiconductor Corp. |
15:25 |
4B-1 |
Strained-Silicon MOSFETs of Low Leakage Current and High Breakdown Voltage for Analog Applications |
|
Abstract
|
N. Sugii, M. Kondo*, M. Miyamoto, Y. Hoshino*,
M. Hatori*, W. Hirasawa**, Y. Kimura, S. Kimura,
Y. Kondo* and I. Yoshida* |
| Hitachi, Ltd., *Renesas Technology Corp. and **Renesas Eastern Japan Semiconductor, Inc., Japan |
15:50 |
4B-2 |
High Capacitance Density (> 17 fF/µm2) Nb2O5-Based MIM Capacitors for Future RF IC Applications |
|
Abstract
|
S.-J. Kim*, B.J. Cho*, M.B. Yu**, M.-F. Li*, **,
Y.-Z. Xiong**, C. Zhu*, A. Chin* and D.-L. Kwong** |
| *National University of Singapore and **Institute of Microelectronics (IME), Singapore |
16:15 |
4B-3 |
HfSiON Gate Dielectrics Design for Mixed Signal CMOS |
|
Abstract
|
K. Kojima, R. Iijima, T. Ohguro, T. Watanabe,
M. Takayanagi, H.S. Momose, K. Ishimaru and
H. Ishiuchi |
| Toshiba Corporation, Japan |
16:40 |
4B-4 |
A Low-Cost 90nm RF-CMOS Platform For Record RF Circuit Performance |
|
Abstract
|
W. Jeamsaksiri, D. Linten, S. Thijs, G. Carchon,
J. Ramos, A. Mercha, X. Sun, P. Soussan, M. Dehan, T. Chiarella, R. Venegas, V. Subramanian,
A. Scholten***, P. Wambacq*, R. Velghe****,
G. Mannaert, N. Heylen, R. Verbeeck, W. Boullart,
I. Heyvaert, M.I. Natarajan, G. Groeseneken**,
I. Debusschere, S. Biesemans and S. Decoutere |
| IMEC, *VUB, **KU Leuven, Belgium, ***Philips Research Labs, Netherlands and ****Philips Research Leuven, Belgium |
17:05 |
4B-5 |
Very High κ and High Density TiTaO MIM Capacitors for Analog and RF Applications |
|
Abstract
|
K.C. Chiang*, A. Chin*,**, C.H. Lai*, W.J. Chen***, C.F. Cheng*, B.F. Hung* and C.C. Liao* |
| *Nat'l Chiao-Tung Univ., Taiwan, ROC, **National Univ. of Singapore, Singapore and ***National PT University of Science and Technology, Taiwan, ROC |
Session 5A |
FUSI Metal Gate Technology [Shunju I] |
| Chairpersons |
H. Oyamatsu, Toshiba Corp.
J. Chen, Freescale Semiconductor |
8:30 |
5A-1 |
A Comprehensive Study of Fully-Silicided Gates to Achieve Wide-range Work Function Differences (0.91 eV) for High-performance CMOS Devices |
|
Abstract
|
K. Hosaka, T. Kurahashi, K. Kawamura*, T. Aoyama, Y. Mishima, K. Suzuki and S. Sato |
| Fujitsu Laboratories Ltd. and *Fujitsu Limited, Japan |
8:55 |
5A-2 |
Highly Reliable HfSiON CMOSFET with Phase Controlled NiSi (NFET) and Ni3Si (PFET) FUSI Gate Electrode |
|
Abstract
|
M. Terai, K. Takahashi, K. Manabe, T. Hase, T. Ogura, M. Saitoh, T. Iwamoto, T. Tatsumi and H. Watanabe |
| NEC Corporation, Japan |
9:20 |
5A-3 |
Fermi Level Pinning Engineering by Al Compositional Modulation and Doped Partial Silicide for HfAlOx(N) CMOSFETs |
|
Abstract
|
M. Kadoshima, A. Ogawa, M. Takahashi, H. Ota*,
N. Mise, K. Iwamoto, S. Migita*, H. Fujiwara,
H. Satake, T. Nabatame and A. Toriumi*,** |
| MIRAI-ASET, *MIRAI-ASRC and **The University of Tokyo, Japan |
9:45 |
5A-4 |
Scalability of Ni FUSI Gate Processes: Phase and Vt Control to 30 nm Gate Lengths |
|
Abstract
|
J.A. Kittl*, A. Veloso, A. Lauwers, K.G. Anil,
C. Demeurisse, S. Kubicek, M. Niwa**, M.J.H. van Dal***, O. Richard, M.A. Pawlak, M. Jurczak, C. Vrancken,
T. Chiarella, S. Brus, K. Maex and S. Biesemans |
| IMEC, *Texas Instruments, **Matsushita and ***Philips Researh Leuven, Belgium |
Session 5B |
(110) and Ge Channel Transistors [Shunju II] |
| Chairpersons |
N. Nagashima, Sony Corp.
T.-J. King, University of California, Berkeley |
8:30 |
5B-1 |
Superior Mobility Characteristics in (110)-Oriented Ultra Thin Body pMOSFETs with SOI Thickness Less Than 6 nm |
|
Abstract
|
G. Tsutsui, M. Saitoh and T. Hiramoto |
| University of Tokyo, Japan |
8:55 |
5B-2 |
Mobility and CMOS Devices/Circuits on Sub-10nm (110) Ultra Thin Body SOI |
|
Abstract
|
H. Shang, J. Rubino, B. Doris, A. Topol, J. Sleight,
J. Cai, L. Chang, J.A. Ott, J. Kedzierski, K. Chan,
L. Shi, K. Babich, J. Newbury, E. Sikorski, B.N. To,
Y. Zhang, K.W. Guarini and M. Ieong |
| IBM Semiconductor Research and Development Center (SRDC) and IBM, T.J. Watson Research Center, USA |
9:20 |
5B-3 |
A New Strained-SOI/GOI Dual CMOS Technology Based on Local Condensation Technique |
|
Abstract
|
T. Tezuka, S. Nakaharai, Y. Moriyama, N. Hirashita, E. Toyoda*, N. Sugiyama, T. Mizuno**,*** and
S. Takagi**,**** |
| MIRAI-ASET, *Toshiba Ceramics, **MIRAI-AIST, ***Kanagawa Univ. and ****The University of Tokyo, Japan |
9:45 |
5B-4 |
Low Defect Ultra-thin Fully Strained-Ge MOSFET on Relaxed Si with High Mobility and Low Band-To-Band-Tunneling (BTBT) |
|
Abstract
|
T. Krishnamohan*, Z. Krivokapic**, K. Uchida*,***, Y. Nishi* and K.C. Saraswat* |
| *Stanford University, **Advanced Micro Devices,
USA and ***Toshiba Corporation, Japan |
Session 6A |
Gate Dielectric Reliability I [Shunju I] |
| Chairpersons |
R. Yamada, Hitachi Ltd.
F. Nouri, Applied Materials, Inc. |
10:30 |
6A-1 |
A New Observation of the Germanium Outdiffusion Effect on the Hot Carrier and NBTI Reliabilities in Sub-100nm Technology Strained-Si/SiGe CMOS Devices |
|
Abstract
|
S.S. Chung, Y.R. Liu, C.F. Yeh*, S.R. Wu*, C.S. Lai*, T.Y. Chang**, J.H. Ho**, C.Y. Liu**, C.T. Huang**, C.T. Tsai**, W.T. Shiau** and S.W. Sun** |
| National Chiao Tung University, *Chang-Gung University and **United Microelectronics Corporation (UMC), Taiwan |
10:55 |
6A-2 |
Improvement in NBTI by Catalytic-CVD Silicon Nitride for hp-65nm Technology |
|
Abstract
|
M. Yamamura, T. Matsuki*, T. Robata*, T. Watanabe*, S. Inumiya*, K. Torii*, T. Saitou*, H. Amai*, Y. Nara*, M. Kitazoe**, Y. Yuba and Y. Akasaka |
| Osaka Univ, *Semiconductor Leading Edge Technologies, Inc. and **ULVAC, Inc., Japan |
11:20 |
6A-3 |
Investigation of Post-NBTI Stress Recovery in
pMOSFETs by Direct Measurement of Single
Oxide Charge De-Trapping |
|
Abstract
|
C.T. Chan, H.C. Ma, C.J. Tang and T. Wang |
| National Chiao-Tung University, Taiwan |
11:45 |
6A-4 |
Fast and Slow Dynamic NBTI Components in p-
MOSFET with SiON Dielectric and Their Impact
on Device Life-Time and Circuit Application |
|
Abstract
|
T. Yang*,**, M.F. Li*,**, C. Shen*, C.H. Ang***,
C. Zhu*, Y.C. Yeo*, G. Samudra*, S.C. Rustagi**,
M.B. Yu** and D.L. Kwong**,**** |
| *National University of Singapore, **Institute of
Microelectronics, ***Chartered Semiconductor
Manufacturing, Singapore and ****The University of
Texas, USA |
Session 6B |
Advanced Memories I [Shunju II] |
| Chairpersons |
T. Nakamura, Rohm Co., Ltd.
C. Dennison, Ovonyx, Inc. |
10:30 |
6B-1 |
Highly Scalable On-axis Confined Cell Structure
for High Density PRAM Beyond 256Mb |
|
Abstract
|
S.L. Cho, J.H. Yi, Y.H. Ha, B.J. Kuh, C.M. Lee,
J.H. Park, S.D. Nam, H. Horii, B.O. Cho, K.C. Ryoo,
S.O. Park, H.S. Kim, U-I. Chung, J.T. Moon and
B.I. Ryu |
| Samsung Electronics Co., LTD., Korea |
10:55 |
6B-2 |
Highly Reliable 50nm Contact Cell Technology for
256Mb PRAM |
|
Abstract
|
S.J. Ahn, Y.N. Hwang, Y.J. Song, S.H. Lee, S.Y. Lee,
J.H. Park, C.W. Jeong, K.C. Ryoo, J.M. Shin, J.H. Park,
Y. Fai, J.H. Oh, G.H. Koh, G.T. Jeong, S.H. Joo,
S.H. Choi, Y.H. Son, J.C. Shin, Y.T. Kim, H.S. Jeong
and K. Kim |
| Samsung Electronics Co., Ltd, Korea |
11:20 |
6B-3 |
Highly Reliable 50nm-thick PZT Capacitor and
Low Voltage FRAM Device Using
Ir/SrRuO3/MOCVD PZT Capacitor Technology |
|
Abstract
|
D.C. Yoo, B.J. Bae, J.-E. Lim, D.H. Im, S.O. Park,
H.S. Kim, U-I. Chung, J.T. Moon and B.I. Ryu |
| Samsung Electronics Co. Ltd., Korea |
11:45 |
6B-4 |
Sub-1.2V Operational, 0.15µm/12F2 Cell FRAM
Technologies For Next Generation SoC
Applications |
|
Abstract
|
Y.M. Kang, J.-H. Kim, H.J. Joo, S.K. Kang, H.S. Rhie,
J.H. Park, D.Y. Choi, S.G. Oh, B.J. Koo, S.Y. Lee,
H.S. Jeong and K. Kim |
| Samsung Electronics Co. Ltd., Korea |
Session 7A |
Multi-Gate Fin FET Technology [Shunju I] |
| Chairpersons |
M. Masahara, AIST
J. Hutchby, SRC |
13:30 |
7A-1 |
Integration of Tall Triple-Gate Devices with
Inserted-TaxNy Gate in a 0.274µm2 6T-SRAM Cell
and Advanced CMOS Logic Circuits |
|
Abstract
|
L.Witters, N. Collaert, A. Nackaerts, M. Demand,
S. Demuynck, C. Delvaux, A. Lauwers, C. Baerts,
S. Beckx, W. Boullart, S. Brus, B. Degroote,
J.F. de Marneffe, A. Dixit, K. De Meyer*, M. Ercken,
M. Goodwin**, E. Hendrickx, N. Heylen, P. Jaenen,
D. Laidler, P. Leray, S. Locorotondo, M. Maenhoudt,
M. Moelants, I. Pollentier, K. Ronse, R. Rooyackers,
J. Van Aelst, G. Vandenberghe, T. Vandeweyer***,
S. Vanhaelemeersch, M. Van Hove, J. Van Olmen,
S. Verhaegen, J. Versluijs, C. Vrancken, V. Wiaux,
P. Willems, J. Wouters, M. Jurczak and S. Biesemans |
| IMEC, *K.U.Leuven, Belgium, **Texas Instruments
Inc., USA and ***Philips Research Leuven, Belgium |
13:55 |
7A-2 |
Tall Triple-Gate Devices with TiN/HfO2 Gate Stack |
|
Abstract
|
N. Collaert, M. Demand, I. Ferain*****, J. Lisoni,
R. Singanamalla*****, P. Zimmerman*, Y.S. Yim**,
T. Schram, G. Mannaert, M. Goodwin***,
J.C. Hooker****, F. Neuilly****, M.C. Kim**,
K. De Meyer*****, S. De Gendt, W. Boullart,
M. Jurczak and S. Biesemans |
| IMEC, *Intel Corp. c/o IMEC, Belgium, **Samsung
Electronics, Korea, ***Texas Instruments Inc., USA,
****Philips Research Leuven and *****K.U.Leuven,
Belgium |
14:20 |
7A-3 |
Negative Bias Temperature Instability in SOI and
Body-Tied Double-Gate FinFETs |
|
Abstract
|
H. Lee, C.-H. Lee*, D. Park* and Y.-K. Choi |
| Korea Advanced Institute of Science and Technology
and *Samsung Electronics Co., Korea |
14:45 |
7A-4 |
ΩFETs Transistors with TiN Metal Gate and HfO2
Down to 10nm |
|
Abstract
|
C. Jahan, O. Faynot, M. Casse, R. Ritzenthaler,
L. Brevard, L. Tosti, X. Garros, C. Vizioz, F. Allain,
A.M. Papon, H. Dansas, F. Martin, M. Vinet,
B. Guillaumot, A. Toffoli, B. Giffard and S. Deleonibus |
| LETI, France |
Session 7B |
Flash Memory I [Shunju II] |
| Chairpersons |
J.H. Lee, MagnaChip Semiconductor Ltd.
M.-R. Lin, AMD |
13:30 |
7B-1 |
A Novel NAND-Type PHINES Nitride Trapping
Storage Flash Memory Cell With Physically 2-bits-
Per-Cell Storage, and a High Programming
Throughput for Mass Storage Applications |
|
Abstract
|
C.C. Yeh*, T. Wang*, Y.Y. Liao, W.J. Tsai, T.C. Lu,
M.S. Chen, Y.R. Chen, K.F. Chen, Z.T. Han, M.S. Wong,
S.M. Hsu, N.K. Zous, T.F. Ou, W.C. Ting, J. Ku and
C.-Y. Lu |
| Macronix International Co.,Ltd and *National Chiao-
Tung University, Taiwan, ROC |
13:55 |
7B-2 |
Highly Scalable and Reliable 2-bit/cell SONOS
Memory Transistor Beyond 50nm NVM
Technology Using Outer Sidewall Spacer Scheme
with Damascene Gate Process |
|
Abstract
|
B.Y. Choi, B.-G. Park, Y.K. Lee*, S.K. Sung**,
T.Y. Kim**, E.S. Cho**, H.J. Cho**, C.W. Oh**,
S.H. Kim**, D.W. Kim**, C.-H. Lee** and D. Park** |
| Seoul National University, Korea, *Stanford
University, USA and **Samsung Electronics Co.,
Korea |
14:20 |
7B-3 |
Highly Scalable 90nm STI Bounded Twin FlashTM
Cell with Local Interconnect |
|
Abstract
|
N. Nagel, D. Olligs, V. Polei, S. Parascandola,
H. Boubekeur, L. Bach, T. Muller, M. Strassburg,
S. Riedel, P. Kratzert, D. Caspary, J. Deppe, J. Willer,
N. Schulze, T. Mikolajick, K.-H. Kusters, A. Shappir*,
E. Redmard*, I. Bloom* and B. Eitan* |
| Infineon Technologies, Germany and *Saifun
Semiconductors, Israel |
14:45 |
7B-4 |
BAVI-Cell: A Novel High-Speed 50 nm SONOS
Memory with Band-to-Band Tunneling Initiated
Avalanche Injection Mechanism |
|
Abstract
|
J.S. Sim, I.H. Park, S. Cho, T.H. Kim, K.W. Song,
J. Kong, H. Shin, J.D. Lee and B.-G. Park |
| Seoul National University, Korea |
Session 8A |
Advanced CMOS Technology I [Shunju I] |
| Chairpersons |
C.H. Diaz, TSMC
K. DeMeyer, IMEC |
15:25 |
8A-1 |
High Performance 65 nm SOI Technology with
Dual Stress Liner and Low Capacitance SRAM cell |
|
Abstract
|
E. Leobandung, H. Nayakama*, D. Mocuta,
K. Miyamoto**, M. Angyal, H.V. Meer***,
K. McStay, I. Ahsan , S. Allen, A. Azuma**,
M. Belyansky, R.-V. Bentum***, J. Cheng***,
D. Chidambarrao, B. Dirahoui, M. Fukasawa*,
M. Gerhardt***, M. Gribelyuk, S. Halle, H. Harifuchi*,
D. Harmon, J. Heaps-Nelson, H. Hichri, K. Ida*,
M. Inohara**, K. Inoue*, K. Jenkins, T. Kawamura*,
B. Kim, S.-K. Ku, M. Kumar, S. Lane, L. Liebmann,
R. Logan, I. Melville, K. Miyashita**, A. Mocuta,
P. O' Neil, M.-F. Ng***, T. Nogami*, A. Nomura***,
C. Norris, E. Nowak, M. Ono**, S. Panda, C. Penny,
C. Radens, R. Ramachandran, A. Ray, S.-H. Rhee***,
D. Ryan, T. Shinohara*, G. Sudo**, F. Sugaya*,
J. Strane, Y. Tan, L. Tsou, L. Wang, F. Wirbeleit***,
S. Wu, T. Yamashita*, H. Yan, Q. Ye, D. Yoneyama*,
N. Zamdmer, H. Zhong***, H. Zhu, W. Zhu, P. Agnello,
S. Bukofsky, G. Bronner, E. Crabbe, G. Freeman,
S.-F. Huang, T. Ivers, H. Kuroda*, D. McHerron,
J. Pellerin***, Y. Toyoshima**, S. Subbanna,
N.Kepler*** and L. Su |
| IBM System & Technology Group, *Sony Electronics
Inc, **Toshiba America Electronic Components, Inc
and ***Advanced Micro Devices, Inc, USA |
15:50 |
8A-2 |
Stable SRAM Cell Design for the 32 nm Node and
Beyond |
|
Abstract
|
L. Chang, D. M. Fried, J. Hergenrother, J.W. Sleight,
R.H. Dennard, R.K. Montoye, L. Sekaric, S.J. McNab,
A.W. Topol, C.D. Adams, K.W. Guarini and W. Haensch |
| IBM Semiconductor Research and Development
Center (SRDC), USA |
16:15 |
8A-3 |
0.248µm2 and 0.334µm2 Conventional Bulk 6TSRAM
Bit-Cells for 45nm Node Low Cost-General
Purpose Applications |
|
Abstract
|
F. Boeuf , F. Arnaud, C. Boccaccio, F. Salvetti*,
J. Todeschini*, L. Pain**, M. Jurdit**, S. Manakli,
B. Icard**, N. Planes, N. Gierczynski*, S. Denorme,
B. Borot, C. Ortolland*, B. Duriez*, B. Tavel*,
P. Gouraud, M. Broekaart*, V. Dejonghe*, P. Brun**,
F. Guyader, P. Morin, C. Reddy***, M. Aminpur***,
C. Laviron**, S. Smith***, J.P. Jacquemin*, M. Mellier*,
F. Andre , N. Bicais-Lepinay, S. Jullian*, J. Bustos
and T. Skotnicki |
| STMicroelectronics, *Philips Semiconductor, **CEALETI
and ***Freescale Semiconductor, France |
16:40 |
8A-4 |
Advantages of Gate Work-Function Engineering by
Incorporating Sub-Monolayer Hf at SiON/poly-Si
Interface in Low-Power CMOS |
|
Abstract
|
Y. Shimamoto, J. Yugami*, M. Inoue*, M. Mizutani*,
T. Hayashi*, K. Shiga*, F. Fujita*, M. Yoneda* and
H. Matsuoka |
| Hitachi Ltd. and *Renesas Technology Corp., Japan |
17:05 |
8A-5 |
Performance of Super-Critical Strained-Si Directly
On Insulator (SC-SSOI) CMOS Based on High-
Performance PD-SOI Technology |
|
Abstract
|
A.V.Y. Thean, T. White, M. Sadaka, L. McCormick,
M. Ramon, R. Mora, P. Beckage, M. Canonico,
X.D. Wang, S. Zollner, S. Murphy, V.Van Der Pas,
M. Zavala, R. Noble, O. Zia, L.-G. Kang, V. Kolagunta,
N. Cave, J. Cheek, M. Mendicino, B.-Y. Nguyen,
M. Orlowski, S. Venkatesan, J. Mogab, C.H. Chang*,
Y.H. Chiu*, H.C. Tuan*, Y.C. See*, M.S. Liang*,
Y.C. Sun*, I. Cayrefourcq**, F. Metral**, M. Kennard**
and C. Mazure** |
| Freescale Semiconductor Inc., USA., *Taiwan
Semiconductor Manufacturing Company, Ltd.
(TSMC)., Taiwan, R.O.C and **SOITEC, France |
Session 8B |
Process Technology [Shunju II] |
| Chairpersons |
H. Tanaka, Oki Electric Industry Co., Ltd.
J. Wu, Texas Instruments |
15:25 |
8B-1 |
Stress Controlled Shallow Trench Isolation
Technology to Suppress the Novel Anti-Isotropic
Impurity Diffusion for 45nm-node High-
Performance CMOSFETs |
|
Abstract
|
K. Ota, T. Yokoyama, H. Kawasaki*, M. Moriya,
T. Kanai, S. Takahashi, T. Sanuki*, E. Hasumi*,
T. Komoguchi, Y. Sogo,Y. Takasu*, K. Eda*, A. Oishi*,
K. Kasai*, K. Ohno, M. Iwai*, M. Saito, F. Matsuoka*,
N. Nagashima, T. Noguchi* and Y. Okamoto |
| Sony Corporation and *Toshiba Corporation, Japan |
15:50 |
8B-2 |
Direct Measurement of Effects of Shallow-Trench
Isolation on Carrier Profiles in Sub-50 nm NMOSFETs |
|
Abstract
|
H. Fukutome, Y. Momiyama*, Y. Tagawa*, T. Kubo*,
T. Aoyama, H. Arimoto* and Y. Nara |
| Fujitsu Laboratories Ltd. and *Fujitsu Limited, Japan |
16:15 |
8B-3 |
Issues and Optimization of Millisecond Anneal
Process for 45 nm Node and Beyond |
|
Abstract
|
K. Adachi, K. Ohuchi, N. Aoki, H. Tsujii, T. Ito,
H. Itokawa, K. Matsuo, K. Suguro, Y. Honguh*,
N. Tamaoki*, K. Ishimaru and H. Ishiuchi |
| Tosiba Corporation Semiconductor Company and
*Toshiba Corporation, Japan |
16:40 |
8B-4 |
Dopant Profile Engineering of CMOS Devices
Formed by Non-Melt Laser Spike Annealing |
|
Abstract
|
A. Shima, Y. Wang*, D. Upadhyaya*, L. Feng*,
S. Talwar* and A. Hiraiwa |
| Hitachi, Ltd., Japan and *Ultratech, Inc., USA |
17:05 |
8B-5 |
Control of Process-Induced Damages in Self-
Assembled Porous Silica /Cu Damascene
Interconnects for 45nm Node and Beyond |
|
Abstract
|
R. Yagi*, S. Chikaki*, M. Shimoyama*, T. Yoshino*,
T. Ono*, A. Ishikawa*, N. Fujii*, N. Hata*, T. Nakayama*,
K. Kohmura*, H. Tanaka*, T. Goto*, J. Kawahara*,
Y. Sonoda*, H. Matsuo*, Y. Seino*, K. Kinoshita*
and T. Kikkawa*, ** |
| *MIRAI and **Hiroshima University, Japan |
Rump Sessions |
| Organizers |
Toru Dan, Sanyo Electric Co., Ltd.
Shahin Sharifzadeh, Cypress Semiconductor |
J-R |
Variability Has Stopped Scaling: Who Will Conquer the
Issues of Variability?
-Will Technology People Be Able to Keep the Device Variability?
-Will Design Technology Take the Further Device Variability Into
Account?
[Suzaku] |
Organizers |
K. Ishibashi, Renesas Technology
H. Masuda, STARC
B. Nikolic, University of California, Berkeley
R. Rakkhit, Cypress Semiconductor
|
Moderators |
H.-S. P. Wong, Stanford University
|
Panelists |
M. Hashimoto, Osaka Univ.
H. Ando, Fujitsu
T. Hiramoto, Univ. of Tokyo
H. Oyamatsu, Toshiba
S. Naffziger, Intel
M. Pelgrom, Philips
C. Wann, IBM
|
|
With further minimization of features in CMOS technology it
becomes apparent that the tolerances on minimum features do not
track scaling of features. There are increasing wafer-to-wafer, chipto-
chip and within-chip variations due to line-width variations, edge
roughness or dopant fluctuations. In order to achieve predictable
product performance there is a need for changes in the requirements
for new devices, circuit designs or tool flows. Should the technology
focus on developing the devices with better control rather than better
average performance? Should the designers be those who absorb the
variability in their designs? Or, will the problem be solved by the
tools that allow for statistical IC design? Our panel of experts will
present their opinions on these topics and discuss the breakthrough
to overcome the issue.
|
R-1 |
Metal Gate: How, When and If? [Shunju]
|
Moderators |
K. Shibahara, Hiroshima University
J. Kedzierski, MIT
|
Panelists |
K. Suguro, Toshiba
U.-I. Chung, Samsung
H. Watanabe, NEC
R. Jammy, IBM
S. Deleonibus, LETI
W. Maszara, AMD
|
Through the elimination of poly-Si depletion, metal-gates can
reduce the equivalent oxide thickness of the gate dielectric by as
much as 0.5 nm. In combination with high-k dielectrics, or stand
alone, metal-gates are considered to be an essential part of future
transistor technologies. Even though metal gates have been utilized
in the beginning of the MOS era, their integration into contemporary
technology has proven challenging. Finding metals with appropriate
and stable workfunctions, and suppressing metal-dielectric
interactions are just some of the challenges that have been
encountered.
This session will address the ‘How, When, and If’ of metal gates.
What is the benefit of using metal-gates? Will metal gates be
implemented in future transistor technologies? If so how? Which
integration strategy will win out, FUSI, metal-first, gate-last? How
will the rest of the device be impacted by the use of a metal gate?
What workfunction range is needed to make metal-gates usable?
Can we use mid-gap or quarter-gap workfunctions for some
applications, or are band-edge workfunctions needed? How will
appropriate workfunctions be achieved? Are the difficulties in
finding stable band-edge metals insurmountable? When will metalgate
technology appear in production? And finally, is the effort to
develop a metal-gate technology worth the expected benefit?
|
R-2 |
Will Planar CMOS End? When? Why? [Shunju] |
Moderators |
K. Ishimaru, Toshiba
M. Rodder, Texas Instruments
|
Panelists |
T. Ghani, Intel
T. Skotnicki, STMicroelectronics
C. Diaz, TSMC
D. Park, Samsung
M. Ieong, IBM
Z. Krivokapic, AMD
H. Wakabayashi, NEC
|
|
Planar CMOS has overcome many purported limits using
evolutionary technologies to enable continued density and
performance scaling. However, according to the ITRS Roadmap,
non-planar (3D) CMOS will need to be introduced in the near-future
instead of planar CMOS. Intensive studies have been carried out for
3D CMOS yet many issues remain. On the other hand, functionality
of the planar structure down to 5-10 nm gate lengths has been
demonstrated. Does this mean that we can extend planar structures to
2020? Do we really need non-planar structures? This rump session
will address the questions of ‘Will Planar CMOS End? When?
Why?’ from the viewpoints of performance, manufacturability, cost,
and circuit design taking into account many applications such as
memory, high-performance MPU, digital consumer ASIC, and
mobile/wireless SoC.
|
Session 9A |
Novel Device Concepts [Shunju I] |
| Chairpersons |
Y. Omura, Kansai University
S. Deleonibus, LETI |
8:30 |
9A-1 |
Sub-25nm Single-Metal Gate CMOS Multi-Bridge-
Channel MOSFET (MBCFET) for High
Performance and Low Power Application |
|
Abstract
|
S.-Y. Lee, E.-J. Yoon, D.-S. Shin, S.-M. Kim, S.-D. Suk,
M.-S. Kim, D.-W. Kim, D. Park, K. Kim and B.-I. Ryu |
| Samsung Electronics Co., Korea |
8:55 |
9A-2 |
A Novel Locally Engineered (111) V-channel
pMOSFET Architecture with Improved Drivability
Characteristics for Low-Standby Power (LSTP)
CMOS Applications |
|
Abstract
|
O. Weber*, P. Scheiblin, R. Ritzenthaler, T. Ernst,
F. Andrieu, F. Ducroquet*, J.-F. Damlencourt, Y. Le Tiec,
A.-M. Papon, H. Dansas, L. Brevard, A. Toffoli,
B. Guillaumot** and S. Deleonibus |
| CEA/DRT-LETI, *LPM and **STMicroelectronics,
France |
9:20 |
9A-3 |
High-Performance 50-nm-Gate-Length Schottky-
Source/Drain MOSFETs with Dopant-Segregation
Junctions |
|
Abstract
|
A. Kinoshita, C. Tanaka, K. Uchida and J. Koga |
| Toshiba Corporation, Japan |
9:45 |
9A-4 |
Strain-Induced Very Low Noise RF MOSFETs on
Flexible Plastic Substrate |
|
Abstract
|
H.L. Kao*, A. Chin*,**, B.F. Hung*, J.M. Lai*, C.F. Lee*,
M.-F. Li**, G.S. Samudra**, C. Zhu**, Z.L. Xia***,
X.Y. Liu*** and J.F. Kang*** |
| *Nat'l Chiao-Tung Univ., Taiwan, ROC, **National
Univ. of Singapore, Singapore and ***Peking
University, China |
Session 9B |
Gate Dielectric Reliability II [Shunju II] |
| Chairpersons |
Y. Tada, Tokyo Electron AT Ltd.
R. Chau, Intel Corp. |
8:30 |
9B-1 |
A Novel Fabrication Process to Downscale SiON
Gate Dielectrics (EOT = 1.06 nm, Jgn = 8.5 A/cm2)
Toward Sub-65nm and Beyond |
|
Abstract
|
Y.R. Wang, Y.W. Ying, C.H. Lung, W.T. Chiang, E. Hsu,
M.F. Lu, C. Lin, R.F. Lou, L.Y. Cheng, C.P. Chen,
M. Chan, O. Cheng, K.T. Huang, S.F. Tzou and S.W. Sun |
| United Microelectronics Corp.(UMC), Taiwan, ROC |
8:55 |
9B-2 |
Quantitative Analysis of Contribution of Initial
Traps to Breakdown in HfAlOX/SiO2 Stacked Gate
Dielectrics |
|
Abstract
|
K. Okada*, H. Ota*, W. Mizubayashi*, H. Satake*,
A. Ogawa*, K. Iwamoto*, T. Horikawa*, T. Nabatame*
and A. Toriumi*,** |
| *AIST and **The University of Tokyo, Japan, |
9:20 |
9B-3 |
Optimization and Reliability Characteristics of
TiO2/HfO2 Multi-metal Dielectric MOSFETs |
|
Abstract
|
S.J. Rhee, H.-S. Kim, C.Y. Kang, C.H. Choi, M. Zhang,
F. Zhu, T. Lee, I. Ok, M.S. Akbar, S.A. Krishnan and
J.C. Lee |
| The University of Texas at Austin, USA |
9:45 |
9B-4 |
Reliability of HfSiON as Gate Dielectric for
Advanced CMOS Technology |
|
Abstract
|
H.C.-H. Wang, C.-W. Tsai, S.-J. Chen, C.-T. Chan,
H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C.H. Diaz,
T. Ong, A.S. Oates, M.-S. Liang and M.-H. Chi |
| Taiwan Semiconductor Manufacturing Company,
Taiwan, ROC |
Session 10A |
Strain Enhanced CMOS II [Shunju I] |
| Chairpersons |
Y. Takao, Fujitsu Ltd.
T. Skotnicki, STMicroelectronics |
10:30 |
10A-1 |
The Impact of Uniaxial Strain Engineering on
Channel Backscattering in Nanoscale MOSFETs |
|
Abstract
|
H.-N. Lin, H.-W. Chen*, C.-H. Ko*, C.-H. Ge*,
H.-C. Lin, T.-Y. Huang, W.-C. Lee* and D.D.Tang* |
| National Chiao-Tung University and *Taiwan
Semiconductor Manufacturing Company Ltd., Taiwan,
ROC |
10:55 |
10A-2 |
Experimental and Comparative Investigation of
Low and High Field Transport in Substrate- and
Process-Induced Strained Nanoscaled MOSFETs |
|
Abstract
|
F. Andrieu*,**, T. Ernst*, F. Lime**, F. Rochette*,**,
K. Romanjek**, S. Barraud*, C. Ravit***, F. Boeuf****,
M. Jurczak*****, M. Casse*, O. Weber*, L. Brevard*,
G. Reimbold*, G. Ghibaudo** and S. Deleonibus* |
| *CEA-LETI, **IMEP, France, ***Philips Research
Leuven, Belgium, ****STMicroelectronics, France
and *****IMEC, Belgium |
11:20 |
10A-3 |
High Current Drive Uniaxially-Strained SGOI
pMOSFETs Fabricated by Lateral Strain
Relaxation Technique |
|
Abstract
|
T. Irisawa*, T. Numata*, T. Tezuka*, K. Usuda*,
N. Hirashita*, N. Sugiyama*, E. Toyoda*** and
S. Takagi**,**** |
| *MIRAI-ASET, **MIRAI-AIST, ***Toshiba Ceramics
and ****The University of Tokyo, Japan |
11:45 |
10A-4 |
Performance Boost of Scaled Si PMOS through
Novel SiGe Stressor for HP CMOS |
|
Abstract
|
D. Chanemougame, S. Monfray, F. Boeuf, A. Talbot,
N. Loubet, F. Payet, V. Fiori, S. Orain*, F. Leverd, D.
Delille*, B. Duriez*, A. Souifi**, D. Dutartre and T.
Skotnicki |
| STMicroelectronics, *Philips Semiconductors and
**UMR-CNRS, France |
Session 10B |
Advanced Memories II [Shunju II] |
| Chairpersons |
T. Nakamura, Rohm Co., Ltd.
C. Dennison, Ovonyx, Inc. |
10:30 |
10B-1 |
Highly Scalable MRAM Using Field Assisted
Current Induced Switching |
|
Abstract
|
W.C. Jeong, J.H. Park, J.H. Oh, G.T. Jeong, H.S. Jeong
and K. Kim |
| Samsung Electronics Co., Ltd., Korea |
10:55 |
10B-2 |
90nm Toggle MRAM Array with 0.29µm2 Cells |
|
Abstract
|
M. Durlam, T. Andre, P. Brown, J. Calder, J. Chan,
R. Cuppens**, R.W. Dave, T. Ditewig**, M. DeHerrera,
B.N. Engel, B. Feil, C. Frey*, D. Galpin*, B. Garni,
G. Grynkewich, J. Janesky, G. Kerszykowski, M. Lien,
J. Martin, J. Nahas, K. Nagel, K. Smith, C. Subramanian,
J.J. Sun, J. Tamim*, R. Williams, L. Wise, S. Zoll*,
F. List**, R. Fournel*, B. Martino and S. Tehrani |
| Freescale Semiconductor, *STMicroelectronics and
**Philips Semiconductor, USA |
11:20 |
10B-3 |
Toggling Cell with Four Antiferromagnetically
Coupled Ferromagnetic Layers for High Density
MRAM with Low Switching Current |
|
Abstract
|
T. Suzuki, Y. Fukumoto, K. Mori, H. Honjo, R. Nebashi,
S. Miura, K. Nagahara, S. Saito, H. Numata, K. Tsuji,
T. Sugibayashi, H. Hada, N. Ishiwata, Y. Asao*,
S. Ikegawa*, H. Yoda* and S. Tahara |
| NEC Corporation and *Toshiba Corporation, Japan |
11:45 |
10B-4 |
Nonvolatile MOSFET Memory Based on High
Density WN Nanocrystal Layer Fabricated by
Novel PNL (Pulsed Nucleation Layer) Method |
|
Abstract
|
S.-H. Lim, K.H. Joo, J.-H. Park, S.-W. Lee, W.H. Sohn,
C. Lee, G.H. Choi, I.-S. Yeo, U-I. Chung, J.T. Moon
and B.-I. Ryu |
| Samsung Electronics Co., Ltd., Korea |
Session 11A |
Advanced Fin FET Technology [Shunju I] |
| Chairpersons |
T. Hiramoto, University of Tokyo
A. Lacaita, Politecnico di Milano |
13:30 |
11A-1 |
25% Drive Current Improvement for p-type
Multiple Gate FET (MuGFET) Devices by the
Introduction of Recessed Si0.8Ge0.2 in the Source and
Drain Regions. |
|
Abstract
|
P. Verheyen, N. Collaert, R. Rooyackers, R. Loo,
D. Shamiryan, A. De Keersgieter, G. Eneman*,**,
F. Leys, A Dixit*, M.Goodwin***, Y.S.Yim****,
M. Caymax, K. De Meyer*, P. Absil, M. Jurczak and
S. Biesemans |
| IMEC, *ESAT-INSYS, **Fund for Scientific Research,
***Texas Instruments and ****Samsung, Belgium |
13:55 |
11A-2 |
Fully Working High Performance Multi-Channel
Field Effect Transistor (McFET) SRAM Cell on
Bulk Si Substrate Using TiN Single Metal Gate |
|
Abstract
|
S.M. Kim, E.J. Yoon, M.S. Kim, C.W. Oh, S.D. Suk,
M. Li, S.Y. Lee, K.H. Yeo, S.H. Kim, D.U. Choe,
D.-W. Kim, D. Park, K. Kim and B.-I. Ryu |
| Samsung Electronics Co., Korea |
14:20 |
11A-3 |
CMP-less integration of Fully Ni-Silicided Metal
Gates in FinFETs by Simultaneous Silicidation of
the Source, Drain, and the Gate Using a Novel Dual
Hard Mask Approach |
|
Abstract
|
K. G. Anil*, P. Verheyen*, N. Collaert*, A. Dixit*,**,
B. Kaczer*, J. Snow*, R. Vos*, S. Locorotondo*,
B. Degroote*, X. Shi*, R. Rooyackers*, G. Mannaert*,
S. Brus*, Y. S. Yim***, A. Lauwers*, M. Goodwin****,
J. A. Kittl****, M. van Dal*****, O. Richard*,
A. Veloso*, S. Kubicek*, S. Beckx*, W. Boullart*,
K. De Meyer*,**, P. Absil*, M. Jurczak* and
S. Biesemans* |
| *Interuniversity Microelectronics Center (IMEC),
**K.U. Leuven, ***Samsung Electronics, ****Texas
Instruments and *****Philips Research at IMEC,
Belgium |
14:45 |
11A-4 |
Multiple Independent Gate Field Effect Transistor
(MIGFET)-Multi-Fin RF Mixer Architecture,
Three Independent Gates (MIGFET-T) Operation
and Temperature Characteristics |
|
Abstract
|
L. Mathew, Y. Du, S. Kalpat, M. Sadd, M. Zavala,
T. Stephens, R. Mora, R. Rai, S. Becker, C. Parker,
D. Sing, R. Shimer, J. Sanez, A.V.-Y. Thean, L. Prabhu,
M. Moosa, B.-Y. Nguyen, J. Mogab, G.O. Workman,
A. Vandooren, Z. Shi, M.M. Chowdhury*, W. Zhang*
and J.G. Fossum* |
| Freescale Semiconductor Inc. and *University. of
Florida, USA |
Session 11B |
Flash Memory II [Shunju II] |
| Chairpersons |
K. Shibahara, Hiroshima University
S. Sharifzadeh, Cypress Semiconductor |
13:30 |
11B-1 |
Flash ETOXTM Virtual Ground Architecture: A
Future Scaling Direction |
|
Abstract
|
R. Koval, V. Bhachawat, C. Chang, M. Hajra,
D. Kencke, Y. Kim, C. Kuo, T. Parent, M. Wei,
B.J. Woo and A. Fazio |
| Intel Corporation, USA |
13:55 |
11B-2 |
Negative-Source Enhanced Source-Side Injection
Achieving 100-ns Cell Programming in Multilevel
Flash Memories |
|
Abstract
|
T. Kawamura, Y. Sasago, H. Kurata, K. Otsuga,
S. Noda*, K. Kozakai* and T. Kobayashi |
| Hitachi, Ltd. and *Renesas Technology Corp., Japan |
14:20 |
11B-3 |
Hf-silicate Inter-Poly Dielectric Technology for Sub
70nm Body Tied FinFET Flash Memory |
|
Abstract
|
E.S. Cho, C.-H. Lee, T.-Y. Kim, S.-K. Sung, B.K. Cho,
C. Lee, H.J. Cho, Y. Roh*, D. Park, K. Kim and
B.-I. Ryu |
| Samsung Electronics Co. and *Sungkyunkwan
University, South Korea |
14:45 |
11B-4 |
Novel SiO2/AlN/HfAlO/IrO2 Memory with Fast
Erase, Large Δ Vth and Good Retention |
|
Abstract
|
C.H. Lai*,**, A. Chin*,**, K.C. Chiang*, W.J. Yoo**,
C.F. Cheng*, S.P. McAlister***, C.C. Chi**** and
P. Wu* |
| *Nat'l Chiao-Tung Univ., Taiwan, ROC, **National
Univ. of Singapore, Singapore, ***National Research
Council of Canada, Canada and ****National Tsing
Hua Univ., Taiwan, ROC |
Session 12A |
Advanced CMOS Technolgoy II [Shunju I] |
| Chairpersons |
T. Ipposhi, Renesas Technology Corp.
M. Mirabedini, LSI Logic |
15:25 |
12A-1 |
High Performance FDSOI CMOS Technology with
Metal Gate and High-k |
|
Abstract
|
B. Doris, B.P. Linder*, Y.H. Kim*, M. Steen*,
V. Narayanan*, D. Boyd*, J. Rubino*, L. Chang*,
J. Sleight, A. Topol*, K. Wong, K. Babich*, Y. Zhang*,
P. Kirsch, J. Newbury*, G.F. Walker*, P. Kozlowski*,
R. Jammy*, K.W. Guarini* and M. Ieong* |
| IBM Semiconductor Research and Development
Center (SRDC) and *IBM T. J. Watson Research
Center, USA |
15:50 |
12A-2 |
A 65nm Low Power CMOS Platform with 0.495µm2
SRAM for Digital Processing and Mobile
Applications |
|
Abstract
|
K. Utsumi, E. Morifuji, M. Kanda, S. Aota, T. Yoshida,
K. Honda, Y. Matsubara, S. Yamada and F. Matsuoka |
| Toshiba Corporation, Japan |
16:15 |
12A-3 |
Ultra-Low Standby Power (U-LSTP) 65-nm Node
CMOS Technology Utilizing HfSiON Dielectric and
Body-biasing Scheme |
|
Abstract
|
N. Kimizuka, Y. Yasuda, T. Iwamoto*, I. Yamamoto,
K. Takano, Y. Akiyama and K. Imai |
| NEC Electronics Corporation and *NEC Corporation,
Japan |
16:40 |
12A-4 |
Highly Cost Effective and High Performance 65nm
S3 ( Stacked Single-crystal Si) SRAM Technology
with 25F2, 0.16um2 Cell and Doubly Stacked SSTFT
Cell Transistors for Ultra High Density and High
Speed Applications |
|
Abstract
|
S.-M. Jung, Y. Rah, T. Ha, H. Park, C. Chang, S. Lee,
J. Yun , W. Cho, H. Lim, J. Park, J. Jeong, B. Son , J. Jang,
B. Choi, H. Cho and K. Kim |
| Samsung Electronics, Korea |
17:05 |
12A-5 |
Comprehensive Study on Layout Dependence of
Soft Errors in CMOS Latch Circuits and Its
Scaling Trend for 65 nm Technology Node and
Beyond |
|
Abstract
|
H. Fukui, M. Hamaguchi, H. Yoshimura, H. Oyamatsu,
F. Matsuoka, T. Noguchi, T. Hirao*, H. Abe*, S. Onoda*,
T. Yamakawa*, T. Wakasa* and T. Kamiya* |
| Toshiba Corporation and *Japan Atomic Energy
Research Institute, Japan |
Session 12B |
High k Dielectric Technology [Shunju II] |
| Chairpersons |
M. Niwa, Matsushita Electric Industrial Co., Ltd.
K. Schruefer, Infineon Technologies |
15:25 |
12B-1 |
Fabrication of TaN-gated Ultra-Thin MOSFETs
(EOT <1.0nm) with HfO2 using a Novel Oxygen
Scavenging Process for Sub 65nm Application |
|
Abstract
|
C. Choi, C.Y. Kang, S.J. Rhee, M.S. Abkar, S.A. Krishna,
M. Zhang, H. Kim, T. Lee, F. Zhu, I. Ok, S. Koveshnikov*
and J.C. Lee |
| The University of Texas and *Intel Corporation, USA |
15:50 |
12B-2 |
Impact of Electrode-side Chemical Structures on
Electron Mobility in Metal/ HfO2 MISFETs with
Sub-1nm EOT |
|
Abstract
|
Y. Akasaka*, K. Miyagawa*, T. Sasaki*,
K. Shiraishi**,***, S. Kamiyama*, O. Ogawa*,
F. Ootsuka* and Y. Nara* |
| *Semiconductor Leading Edge Technologies, Inc.,
**University of Tsukuba and ***National Institute for
Material Science, Japan |
16:15 |
12B-3 |
Role of Oxygen Vacancies in VFB/Vt Stability of
pFET Metals on HfO2 |
|
Abstract
|
E. Cartier, F. R. McFeely, V. Narayanan, P. Jamison*,
B. P. Linder, M. Copel, V.K. Paruchuri, V.S. Basker,
R. Haight, D. Lim, R. Carruthers, T. Shaw, M. Steen,
J. Sleight*, J. Rubino, H. Deligianni, S. Guha, R. Jammy
and G. Shahidi |
| IBM Semiconductor Research and Development
Center (SRDC) and *IBM Systems and Technology
Division, USA |
16:40 |
12B-4 |
A Highly Manufacturable MIPS (Metal Inserted
Poly-Si Stack) Technology with Novel Threshold
Voltage Control |
|
Abstract
|
H.-S. Jung, J.-H. Lee, S.K. Han, Y.-S. Kim, H.J. Lim,
M.J. Kim, S.J. Doh, M.Y. Yu, N.-I. Lee, H.-L. Lee,
T.-S. Jeon, H.-J. Cho, S.B. Kang, S.Y. Kim, I.S. Park,
D. Kim, H.S. Baik* and Y.S. Chung* |
| Samsung Electronics Co., Ltd., and *Samsung
Advanced Institute of Technology, Korea |
17:05 |
12B-5 |
High Performing 8Å EOT HfO2 / TaN Low
Thermal-Budget n-channel FETs with Solid-Phase
Epitaxially Regrown (SPER) Junctions |
|
Abstract
|
L.-Å. Ragnarsson*, S. Severi*,***, L. Trojman*,***,
D.P. Brunco**, K.D. Johnson**, A. Delabie*,
T. Schram*, W. Tsai**, G. Groeseneken*,***,
K. De Meyer*,***, S. De Gendt*,*** and M. Heyns* |
| *IMEC, **Intel Corp., USA and ***KU Leuven,
Belgium |
|
