Sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics
In Cooperation with the IEEE Solid-State Circuits Society


Hilton Hawaiian Village
Honolulu, Hawaii
June 15 - 17, 2010

Click here for PDF of Call for Papers
The 2010 Symposium on VLSI Technology welcomes the submission of papers on all aspects of VLSI technology. In addition, two new topics are added to the scope of the symposium – “Design Enablement” to encourage submissions from Fabless/Fablite and Foundry companies, and “Heterogeneous Integration” of non-Si substrate/materials on large Si wafers for both Moore’s Law extension and opportunities orthogonal to conventional scaling (More-Than-Moore). These topics will also be addressed in the Focus Sessions.

FOCUS SESSIONS: Two Focus sessions of exclusively invited papers will cover a selection of key developments in the aforementioned two topics. Design Enablement will focus on how new or disruptive device, process and materials technologies will impact circuit design (including design rule restrictions, device models, OPC, DFM...etc), product performance, and product migratability. Heterogeneous Integration will focus on integrating non-Si substrates/materials on large Si wafers (CNT, graphene, Ge, SiGe, III-V...etc), including their process integration, device architectures, performance and impact on CMOS roadmaps.

The scope of the symposium is being expanded into innovative areas such as:

- New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/Mixed-Signal/High-Voltage, Imager, MEMS, etc.)

- Advanced gate stacks and interconnects in VLSI processes and devices

- Advanced lithography and fine-patterning technologies for high-density VLSI

- New functional devices beyond CMOS with a path for VLSI implementation

- Packing of VLSI devices including 3D-system integration

- Advanced device analysis, materials and modeling for VLSIs

- Reliability related to the above devices

- Theories and fundamentals related to the above devices

- New concepts and technologies for VLSI manufacturing

- Design enablement (including technology impacts on circuit design in advanced CMOS nodes)

- Heterogeneous integration of non-Si substrates/materials on Si substrate


Prospective authors must submit papers in the format of two pages of camera-ready copy to the Author's Guide page:

Please note that hard copy submission will NOT be accepted.

Those interested in submitting papers should access the above website.
The papers are to be submitted in final form and, if accepted, will be published as submitted.

To improve the probability for acceptance of a submitted paper, the paper should describe original work with specific results from experiments or simulations. The technical content beyond the abstract of the accepted paper must not be announced, published, or in any way put in the public domain prior to the Symposium.

Submissions from universities are encouraged. Partial travel expense support for students who are presenting papers is available upon request.

The selection will be based upon the quality of the written paper and the presentation. The student who receives the Best Student Paper Award will be presented a monetary award and a certificate at the opening session of the 2011 Symposium. The student must be the leading author and the presenter of the paper, and must indicate in the web submission form that this is a student paper in order to be considered for this award.

Paper Submission Deadline
23:59, January 25, 2010 (PST)

Prospective attendees can obtain further information and forms for registration and hotel reservations from the Symposium website by visiting or from the closest secretariat.

A one-day short course will be held on June 14, 2010. Details will be given in the VLSI Technology Symposium Advance Program, which will be posted on the web around the middle of April, 2010.

2010 Silicon Nanoelectronics Workshop will be held on June 13-14, 2010 at the same location.

Following the first day of this Symposium, the 2010 Symposium on VLSI Circuits will be held at the same location with two days of overlap between the two symposia.

Secretariat for VLSI Symposia (USA)
Widerkehr and Associates
19803 Laurel Valley Place
Montgomery Village,
MD 20886, USA
Tel: +1-301-527-0900 ext.2
Fax: +1-301-527-0994
Secretariat for VLSI Symposia (Japan)
c/o ICS Convention Design, Inc.
Chiyoda Bldg. 1-5-18 Sarugakucho
Chiyoda-ku, Tokyo 101-8449, Japan
Tel: +81-3-3219-3541
Fax: +81-3-3219-3626

Call for papersTechnical ProgramShort CoursesCommitteesBest Student Paper Award
Best Student Paper AwardShort CoursesCall For PapersTechnical Programcommittees