Former Best Student Paper Award Winners – Symposium on VLSI Circuits

2015

Recipient:
Abishek Manian
Paper:
A 40-Gb/s 9.2-mW CMOS Equalizer
Authors:
A. Manian and B. Razavi
Affiliation:
University of California, Los Angeles
2014

Recipient:
Maryam Tabesh
Paper:
A Power-Harvesting Pad-Less mm-Sized 24/60GHz Passive Radio with On-Chip Antennas
Authors:
Maryam Tabesh, Mustafa Rangwala*, Ali M. Niknejad and Amin Arbabian*
Affiliation:
University of California, Berkeley and *Stanford University
2013

Recipient:
Yingzhe Hu
Paper:
A Fully Self-Powered Hybrid System Based on CMOS ICs and Large-Area Electronics for Large-Scale Strain Monitoring
Authors:
Yingzhe Hu, Liechao Huang, Josue Sanz Robinson, Warren Rieutort-Louis, Sigurd Wanger, James C. Sturm, Naveen Verma
Affiliation:
Princeton University, USA
2012

Recipient:
Jun Won Jung
Paper:
A 25-Gb/s 5-mW CMOS CDR/Deserializer
Authors:
Jun Won Jung and Behzad Razavi
Affiliation:
University of California, Los Angeles, CA, USA
2011

Recipient:
Chintan Thakkar
Paper:
A 10Gb/s 45mW Adaptive 60GHz Baseband in 65nm CMOS
Authors:
Chintan Thakkar1, Lingkai Kong1, Kwangmo Jung1, Antoine Frappé2, and Elad Alon1
Affiliation:
1University of California, Berkeley, USA & 2Institut Supérieur de l'Electronique et du Numérique, France
2010

Recipient:
Dajiang Zhou
Paper:
A 530Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip
Authors:
Dajiang Zhou1, Jinjia Zhou1, Xun He1, Ji Kong2, Jiayi Zhu2, Peilin Liu2, and Satoshi Goto1
Affiliation:
1Waseda University, Japan & 2Shanghai Jiao Tong University, China
2009

Recipient:
Zhengya Zhang
Paper:
A 47 Gb/s LDPC Decoder with Improved Low Error Rate Performance
Authors:
Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic
Affiliation:
University of California, Berkeley, USA
2008

Recipient:
Jason Hu
Paper:
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC using Dynamic Residue Amplification
Authors:
Jason Hu, Noam Dolev and Boris Murmann
Affiliation:
Stanford University, USA
2007

Recipient:
Minjae Lee
Paper:
A 9b, 1.25ps Resolution Coarse-Fine Time-to- Digital Converter in 90nm CMOS that Amplifies a Time Residue
Authors:
Minjae Lee and Asad A. Abidi
Affiliation:
University of California, Los Angeles, USA
2006

Recipient:
Koon-Lun Jackie Wong
Paper:
A 5-mW 6-Gb/s Quarter-Rate Sampling receiver with a 2-Tap DFE Using Soft Decisions
Authors:
Koon-Lun Jackie Wong1, Alexander Rylyakov2, and Chih-Kong Ken Yang1
Affiliation:
1University of California, Los Angeles, USA & 2IBM T. J. Watson Research Center, USA
2005

Recipient:
Antonio Liscidini
Paper:
A 0.13 um CMOS Front-End for DCS1800/UMTS/ 802.11b-g with Multi-band Positive Feedback Low Noise Amplifier
Authors:
Antonio Liscidini, Massimo Brandolini, Davide Sanzogni, and Rinaldo Castello
Affiliation:
University of Pavia, Italy
2004

Recipient:
Timothy O. Dickson
Paper:
A 2.5-V, 40-Gb/s Decision Circuit Using SiGe BiCMOS Logic
Authors:
Timothy O. Dickson1, Rudy Beerkens2, and Sorin P. Voinigescu1
Affiliation:
1University of Toronto, Canada & 2STMicroelectonics, Canada