2005 SYMPOSIUM ON VLSI CIRCUITS

Welcome to the 2005 Symposium on VLSI Circuits

You are cordially invited to attend the 2005 Symposium on VLSI Circuits, to be held on June 16-18th, 2005, at the Rhiga Royal Hotel Kyoto in Kyoto, Japan. Following the tradition of the last several years, the Symposium on VLSI Circuits will follow the Symposium on VLSI Technology at the same location.

The Symposium will mark its 19th anniversary. The Symposium has established itself as a major international forum for presenting and exchanging important ideas and new developments in VLSI circuit design. We have expanded the scope to include new concepts in VLSI, such as MEMS, novel Memory, and Quantum Computing, in addition to the traditional Analog, Digital, Memory, Signal Processing, and Communications circuits. Contributions to the Symposium come from both industry and academia around the world.

Preceding the Symposium on June 15th, a one-day Short Course on VLSI circuits will be held. This short course will focus on “Multi- GHz Clocking Technologies for Microprocessors” where six wellknown experts will give talks on advanced techniques for clock generation, distribution, and synchronization.

This year, the technical program committee reviewed 259 papers, and selected 92 papers for presentation. These papers disclose new and interesting circuit design concepts for digital, memory, analog, wireless, and wireline circuits.

We have also invited four distinguished speakers to describe recent advances and new challenges related to VLSI circuits and technology in the areas of entertainment robotics, Ultra Wide Band (UWB) wireless communications, integrated circuits for the robotics exploration of the solar system, and Flash Memory for mobile/consumer applications.

To complement the formal talks, we have arranged four evening rump sessions on interesting and provocative subjects to give you an opportunity to participate in the discussions and mix with the participants. The rump sessions explore: “Variability has Stopped Scaling: Who will Conquer the Issues of Variability?”, “Low Power Design: Process Puzzle or Design Dilemma?”, “The Roadblock to the TeraBit (1012 bits) Memory Era: Is It Technology or Design?”, and “Digitizing the Radio to the Antenna - Will Radios Still Need Analog in 2010?”.

The rich technical content of the program will undoubtedly interest you, and we certainly hope that the Symposium will be a fruitful and enjoyable experience.

This booklet contains the advance program together with forms for the Symposium registration and hotel reservations. Please complete and return these forms or visit our website for online registration at /20web/symposia.html. Although on-site registration will be available at the conference, pre-registration will facilitate Symposium planning.

We look forward to meeting with you at the Symposium in Kyoto.



Tadahiro Kuroda

Stephen Kosonocky
Program Chair Program Co-Chair




CONFERENCE SCHEDULE


Tuesday, June 14

8:00-17:00

Registration
Wednesday, June 15 7:00 Breakfast
8:00 Registration
8:40-12:20 Short Course [Suzaku]
14:00-16:50 Short Course [Suzaku]
18:00-20:00 Reception [Suzaku I]
20:00-22:00 Technology and Circuits Joint Rump Session [Suzaku, Shunju]
Thursday, June 16 7:00 Breakfast
8:00 Registration
8:30-10:15 Session 1 Welcome and Plenary Session I [Suzaku]
10:30-12:10 Session 2 Microprocessor [Suzaku I, II]
Session 3 Ultra-Wideband Techniques [Suzaku III]
13:50-15:30 Session 4 PLLs [Suzaku I]
Session 5 Imagers, Biochip and MEMS [Suzaku II]
Session 6 RF Building Blocks [Suzaku III]
15:50-17:30 Session 7 PLL and On-Chip Interconnect [Suzaku I]
Session 8 Analog Techniques [Suzaku II]
Session 9 Multi-GHz Wireline Building Blocks [Suzaku III]
20:00-22:00 Rump Sessions [Suzaku I,II,III]
Friday, June 17 7:00 Breakfast
8:30-10:00 Session 10 Plenary Session II [Shunju]
10:30-12:10 Session 11 SRAM and NV-memory [Shunju I]
Session 12 High Quality Audio Chips [Shunju II]
Session 13 High Speed I/O's [Shunju III]
13:50-15:30 Session 14 Signal Processors [Shunju I]
Session 15 Drivers and Sensors [Shunju II]
Session 16 Oscillators and PLLs [Shunju III]
15:50-17:30 Session 17 Digital Blocks [Shunju I]
Session 18 Substrate Analysis and Devices [Shunju II]
Session 19 WLAN RF ICs [Shunju III]
18:00-20:00 Dinner [Suzaku]
Saturday, June 18 7:00 Breakfast
8:30-10:10 Session 20 Low Power Design [Shunju I]
Session 21 Data Converters [Shunju II]
Session 22 DTV Tuner and Wireless Interconnect Techniques [Shunju III]
10:30-12:10 Session 23 Emerging DRAMs [Shunju I]
Session 24 Wireline Receivers and Transmitters [Shunju II]
Session 25 Cellular RF ICs [Shunju III]




PROGRAM


Wedensday, June 15
20:00-22:00

Joint Rump Session with Technology

J-R

Variability Has Stopped Scaling: Who Will Conquer the Issues of Variability?
-Will Technology People Be Able to Keep the Device Variability?
-Will Design Technology Take the Further Device Variability into Account?
Organizers   K. Ishibashi,   Renesas Technology
  H. Masuda,   STARC
  B. Nikolic,   University of California, Berkeley
  R. Rakkhit,   Cypress Semiconductor
Moderators   H.-S.P. Wong,   Stanford University

Panelists

  M. Hashimoto,   Osaka Univ.
  H. Ando,   Fujitsu
  T. Hiramoto,   Univ. of Tokyo
  H. Oyamatsu,   Toshiba
  S. Naffziger,   Intel
  M. Pelgrom,   Philips
  C. Wann,   IBM
  With further minimization of features in CMOS technology it becomes apparent that the tolerances on minimum features do not track scaling of features. There are increasing wafer-to-wafer, chipto- chip and within-chip variations due to line-width variations, edge roughness or dopant fluctuations. In order to achieve predictable product performance there is a need for changes in the requirements for new devices, circuit designs or tool flows. Should the technology focus on developing the devices with better control rather than better average performance? Should the designers be those who absorb the variability in their designs? Or, will the problem be solved by the tools that allow for statistical IC design? Our panel of experts will present their opinions on these topics and discuss the breakthrough to overcome the issue.
back to conference schedule
Thursday, June 16

Session 1

Welcome and Plenary Session I [Suzaku]
Chairpersons T. Kuroda, Keio Univ.
S. Kosonocky, IBM

8:30

1-1
Welcome and Opening Remarks
   T. Nishimura, Renesas Technology
B. Gieseke, AMD

8:45

1-2
Development of Entertainment Robot and Its Future (Invited)
   K. Sabe, Sony Intelligence Dynamics Laboratories, Inc.

9:30

1-3
Ultra Wide Bandwidth (UWB): Gigabit Wireless Communications for Battery Operated Consumer Applications (Invited)
   J. McCorkle, Freescale Semiconductor
back to conference schedule
(Break 10:15-10:30)
Thursday, June 16

Session 2

Microprocessor [Suzaku I, II]
Chairpersons M. Matsui, Toshiba Corp.
S. Butler, AMD

10:30

2-1
A 1.5 GHz 90 nm Embedded Microprocessor Core
Abstract   F. Ricci, L.T. Clark*, T. Beatty, W. Yu, A. Bashmakov, S. Demmons, E. Fox, J. Miller, M. Biyani and J. Haigh
Intel Corporation and *Arizona State University, USA

10:55

2-2
Enhancing Microprocessor Immunity to Power Supply Noise with Clock/Data Compensation
Abstract   T. Rahal-Arabi, G. Taylor, J. Barkatullah, K.L. Wong and M. Ma
Intel Corporation, USA

11:20

2-3
The Circuits and Physical Design of the Synergistic Processor Element of a CELL Processor
Abstract   O. Takahashi, R. Cook, S. Cottier, S.H. Dhong, B. Flachs, K. Hirairi****, A. Kawasumi*****, H. Murakami*****, H. Murakami*****, H. Noro*****, H. Oh, S. Onishi*, J. Pille**, J. Silberman*** and S. Yong
IBM Systems and Technology Group, USA, *IBM Engineering and Technology Services, Japan, **IBM Entwicklung GmbH, Germany, ***IBM T.J. Watson Research Center, ****Sony Computer Entertainment of America and *****Toshiba America Electronic Components, USA

11:45

2-4
A Fully-Pipelined Single-Precision Floating Point Unit in the Synergistic Processor Element of a CELL Processor
Abstract   H.-J. Oh, S.M. Mueller*, C. Jacobi*, K.D. Tran, S.R. Cottier, B.W. Michael, H. Nishikawa**, Y. Totsuka***, T. Namatame****, N. Yano****, T. Machida**** and S.H. Dhong
IBM System and Technology Group, USA, *IBM Entwicklung GmbH, Germany, **IBM Engineering and Technology Services, Japan, ***Sony Computer Entertainment of America and ****Toshiba America Electronic Components, USA
back to conference schedule
(Lunch 12:10-13:50)
Thursday, June 16

Session 3

Ultra-Wideband Techniques [Suzaku III]
Chairpersons T. Kamei, Oki Electric Industry Co., Ltd.
M. Huang, Freescale Semiconductor

10:30

3-1
A CMOS Impulse Radio Ultra-Wideband Transceiver for 1Mb/s Data Communications and ±2.5cm Range Findings
Abstract   T. Terada, S. Yoshizumi, Y. Sanada and T. Kuroda
Keio University, Japan

10:55

3-2
A Miller Divider Based Clock Generator for MBOA-UWB Application
Abstract   T.-C. Lee and Y.-C. Huang
National Taiwan University, Taiwan

11:20

3-3
Subharmonic Direct Frequency Synthesizer for Mode-1 MB-OFDM UWB System
Abstract   C.-C. Lin and C.-K. Wang
National Taiwan University, Taiwan

11:45

3-4
A DLL-Based Frequency Multiplier For MBOA-UWB System
Abstract   T.-C. Lee and K.-J. Hsiao
National Taiwan University, Taiwan
back to conference schedule
(Lunch 12:10-13:50)
Thursday, June 16

Session 4

PLLs [Suzaku I]
Chairpersons C. Kim, Samsung Electronics Co., Ltd.
K. Nowka, IBM

13:50

4-1
An Area-Efficient PLL Architecture in 90-nm CMOS
Abstract   P.J. Lim
Nvidia Corporation, USA

14:15

4-2
A 5.0Gbps/pin Packet-Based DRAM with Low Latency Receiver and Process Insensitive PLL
Abstract   J.-H. Choi, Y.-S. Sohn, C.-K. Kim, W.-K. Park, J.-H. Lee, U. Kang, G.-S. Byun, I.-S. Park, B.-C. Kim, H.-S. Hwang, C.-H. Kim and S.-I. Cho
Samsung Electronics Company, Korea

14:40

4-3
A -90dBc@10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit
Abstract   T. Morie, S. Dosho, K. Okamoto, Y. Yamada and K. Sogawa
Matsushita Electric Industrial Co., Ltd, Japan

15:05

4-4
A Direct Digital Frequency Synthesizer with Single-Stage Delta-Sigma Interpolator and Current-Steering DAC
Abstract   W. Ni, F.F. Dai*, Y. Shi and R.C. Jaeger*
Chinese Academy of Sciences, China and *Auburn University, USA
back to conference schedule
(Break 15:30-15:50)
Thursday, June 16

Session 5

Imagers, Biochip and MEMS [Suzaku II]
Chairpersons M. Ikeda, University of Tokyo
S. Natarajan, ATMOS

13:50

5-1
A Sensitivity and Linearity Improvement of a 100 dB Dynamic Range CMOS Image Sensor Using a Lateral Overflow Integration Capacitor
Abstract   N. Akahane, S. Sugawa, S. Adachi*, K. Mori*, T. Ishiuchi* and K. Mizobuchi*
Tohoku University and *Texas Instruments Japan, Japan

14:15

5-2
The 1T Photo Pixel Cell Using the Tunneling Field Effect Transistor (TFET)
Abstract   T. Nirschl*,**, A. Bargagli-Stoffi*, J. Fischer*, S. Henzler*, P.-F. Wang*,**, M. Sterkel*, W. Hansch* and D. Schmitt-Landsiedel*
*Technical University Munich and **Infineon Technologies, Germany

14:40

5-3
Active CMOS Biochip for Time-Resolved Fluorescence Detection
Abstract   G. Patounakis, K.L. Shepard and R. Levicky
Columbia University, USA

15:05

5-4
A High-Voltage CMOS VLSI Programmable Fluidic Processor Chip
Abstract   K. Current, K. Yuk, C. McConaghy*, P. Gascoyne**, J. Schwartz**, J. Vykoukal** and C. Andrews***
University of California, *Lawrence Livermore National Laboratory, **University of Texas and ***Lynntech, Inc., USA
back to conference schedule
(Break 15:30-15:50)
Thursday, June 16

Session 6

RF Building Blocks [Suzaku III]
Chairpersons H. Sato, Renesas Technology Corp.
T. Blalock, University of Virginia

13:50

6-1
Low Power Programmable-Gain CMOS Distributed LNA for Ultra-Wideband Applications
Abstract   F. Zhang and P. Kinget
Columbia University, USA

14:15

6-2
A Phase-Coherent Transformer Enabled 2:1 Frequency Divider with 7dB Phase Noise Reduction and Speed×Gain/Power F.O.M. of 2×102  (pico- Joule)-1
Abstract   D. Huang*, W. Hant*, W.-K. Yeh*, J.-K. Ma***, C. Chien*,** and M.F. Chang*
*University of California at Los Angeles, **SST Communications Corp., USA and ***Industrial Technology Research Institute, Taiwan

14:40

6-3
An Integrated 5 GHz Low-Noise Amplifier with 5.5 kV HBM ESD Protection in 90 nm RF CMOS
Abstract   D. Linten*, S. Thijs, W. Jeamsaksiri, J. Ramos, A. Mercha, M.I. Natarajan, P. Wambacq*, A.J. Scholten** and S. Decoutere
Inter-university Micro-Electronics Center (IMEC), *the Vrije Universiteit Brussel, Belgium and **Philips Research, Netherlands

15:05

6-4
A DC-2.5GHz Wide Dynamic-Range Attenuator in 0.13µm CMOS Technology
Abstract   H. Dogan, R.G. Meyer and A.M. Niknejad
University of California, USA
back to conference schedule
(Break 15:30-15:50)
Thursday, June 16

Session 7

PLL and On-Chip Interconnect [Suzaku I]
Chairpersons M. Matsui, Toshiba Corp.
V. De, Intel Corp.

15:50

7-1
A Spread Spectrum Clock Generation PLL with Dualtone Modulation Profile
Abstract   D.-S. Kim and D.-K. Jeong
Seoul National University, Korea

16:15

7-2
4.0GHz 0.18µm CMOS PLL Based on an Interpolative Oscillator
Abstract   F.H. Gebara, J.D. Schaub*, A.J. Drake*, K.J. Nowka* and R.B. Brown**
University of Michigan, *IBM Austin Research Lab, and **University of Utah, USA

16:40

7-3
Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme
Abstract   S.-J. Lee, K. Kim, H. Kim, N. Cho and H.-J. Yoo
KAIST, Korea

17:05

7-4
Near Speed-of-Light On-Chip Interconnects Using Pulsed Current-Mode Signalling
Abstract   A.P. Jose, G. Patounakis and K.L. Shepard
Columbia University, USA
back to conference schedule
Thursday, June 16

Session 8

Analog Techniques [Suzaku II]
Chairpersons M. Nagata, Kobe University
P. Kinget, Columbia University

15:50

8-1
An All CMOS 84dB-Linear Low-Power Variable Gain Amplifier
Abstract   Q.-H. Duong, L.-Quan and S.-G. Lee
Information and Communications University, Korea

16:15

8-2
A 1V Supply 50nV/√Hz Noise PSD CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
Abstract   T. Yoshida, Y. Masui, T. Mashimo, M. Sasaki and A. Iwata
Hiroshima University, Japan

16:40

8-3
Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch (AT-Switch) and Super Cut-off CMOS
Abstract   K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi and T. Sakurai
University of Tokyo, Japan

17:05

8-4
A CMOS Oversampling D/A Converter with Multibit Semi-Digital Filtering and Boosted Subcarrier SNR for ADSL Central Office Modems
Abstract   A.C.Y. Lin, D.K. Su, R.K. Hester* and B.A. Wooley
Stanford University and *Texas Instruments Inc., USA
back to conference schedule
Thursday, June 16

Session 9

Multi-GHz Wireline Building Blocks [Suzaku III]
Chairpersons N. Lu, Etron Technology, Inc.
W. Lee, Texas Instruments

15:50

9-1
A 34Gb/s 2:1 MUX/CMU Based on a Distributed Amplifier Using 0.18µm CMOS
Abstract   U. Singh, L. Li and M.M. Green
University of California, Irvine, USA

16:15

9-2
A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-µm CMOS Technology
Abstract   J. Lee, J.-Y. Ding and T.-Y. Cheng
National Taiwan University, Taiwan

16:40

9-3
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-µm CMOS Technology
Abstract   J. Lee and S. Wu
National Taiwan University, Taiwan

17:05

9-4
A 20-GHz Phase-Locked Loop for 40Gb/s Serializing Transmitter in 0.13µm CMOS
Abstract   J. Kim, J.-K. Kim, B.-J. Lee, N. Kim*, D.-K. Jeong and W. Kim
Seoul National University, Korea and *Silicon Image, Inc., USA
back to conference schedule
Thursday, June 16
20:00

Rump Sessions

Organizers
Mamoru Ugajin, NTT
C.K. Ken Yang, UCLA
R-1 Digital Rump Session
Low Power Design: Process Puzzle or Design Dilemma? [Suzaku I]

Organizer
  Y. Oowaki,   Toshiba
  J. Farrell,   AMD

Moderator
  S. Borkar,   Intel

Panelists
  K. Imai,   NEC Electronics
  H. Mizuno,   Hitachi
  D. Scott,   Texas Instruments
  T. Hook,   IBM
  R. Stephany,   AMD
  C. Diaz,   TSMC
  In all designs today, whether it is a high-end microprocessor for servers, or cell phone DSP, power reduction is a priority goal for the design team.
  The previous decades have seen a steady increase in transistor performance despite an equivalent reduction in supply voltages. Is this a trend that the design teams can continue to count on? An accompanying increase in leakage currents has required new design techniques to minimize the impact.
  Will body-biasing, footer transistors, Vt substitution, and other design tricks allow circuit designers to meet their goals using transistors that are more like resistors? The panel will consider the roadmap of future devices and debate if technology can deliver the types of transistors and memory elements that can be used for thermally-challenged microprocessors and battery-limited consumer products. Techniques will be debated on their merits for high-power vs low-power products or memory-intensive vs logic-dominated designs.

R-2
Memory Rump Session
The Roadblock to the TeraBit (1012 bits) Memory Era: Is it Technology or Design? [Suzaku II]

Organizers
  T. Ishii,   Hitachi
  H. Pon,   Intel

Moderator
  A. Fazio,   Intel

Panelists
  K.-N. Kim,   Samsung
  B. Stipe,   Hitachi Global Storage
  S. Tanaka,   Matsushita
  E. Elefheriou,   IBM
  M.N. Kozicki,   Axon
  The density of non-volatile memory will reach 100Gb/chip by 2010 based on current scaling estimates. A new era of terabit non-volatile memory is approaching that promises 1 terabit (1012 bits) of nonvolatile memory that can store 200 CD's, or 25 DVD's, or about 2,000 hours of MP3 music, but what is the delay? Are the current non-volatile memory incumbents of Flash, optical, and magnetic drive memory systems availability, technology scaling, and even resources weighing down the progress of the next revolutionary terabit memory solutions? Or is it the design resources, methodologies, and CAD tools that are holding back the progress of terabit memory solutions? The evening panel discussion allows the memory technology design incumbents and the terabit-class memory technologist to square off and determine which side is to blame for the wait, the technological development or design, and which technology will lead the way.

R-3
Analog Rump Session
Digitizing the Radio to the Antenna - Will Radios Still Need Analog in 2010? [Suzaku III]
Organizers   A. Matsuzawa,   Tokyo Institute of Technology
  M. Huang,   Freescale
Moderator   P. Kinget,   Columbia University

Panelists
  T. Arnaud,   STMicroelectronics
  Q. Huang,   Swiss Federal Institute of Technology
  C.-M. Hung,   Texas Instruments
  H. Kobayashi,   Gunma University
  I. Mehr,   Analog Devices
  S. Tanaka,   Hitachi
  It is becoming more challenging to maintain analog circuit performance and yield as device technology is scaled. Some scaling trends that significantly impact analog circuits include: reduction in supply voltage, decreased GmRo ratio, increased device leakage, and the impact of high-k gate dielectric materials and non-planar device structures on 1/f noise and transistor matching. Additionally, the inability to scale the area of passive components such as capacitors and inductors makes it progressively more and more expensive to incorporate analog functions on digital heavy mixed signal chips such as communication transceivers.
  Recent research on replacing traditional analog and RF functions with digital circuits holds out the promise of a low-cost, single chip, all CMOS digital radio supporting multiple standards. Can the radio function indeed be “digitized” up to the antenna? How to realize such a radio? Or are analog and RF functions such as low noise amplifiers, mixers and filters, irreplaceable by digital circuits?
back to conference schedule
Friday, June 17

Session 10

Plenary Session II [Shunju]
Chairpersons T. Kuroda, Keio University
S. Kosonocky, IBM

8:30

10-1
Design Challenges and Methodology for Developing New Integrated Circuits for the Robotics Exploration of the Solar System (Invited)
   M. Mojarradi, B. Blalock*, E. Kolawa and R. Johnson**
California Institute of Technology, *University of Tennessee and **Auburn University

9:15

10-2
Non-volatile Memory Technologies for Beyond 2010
   Y. Shin
Samsung Electronics
back to conference schedule
(Break 10:00-10:30)
Friday, June 17

Session 11

SRAM and NV-memory [Shunju I]
Chairpersons T. Kawahara, Hitachi Ltd.
S. Natarajan, ATMOS

10:30

11-1
Experimental Verification of Row-by-Row Variable VDD Scheme Reducing 95% Active Leakage Power of SRAM’s
Abstract   F.R. Saliba, H. Kawaguchi and T. Sakurai
University of Tokyo, Japan

10:55

11-2
A Low Leakage SRAM Macro with Replica Cell Biasing Scheme
Abstract   Y. Takeyama, H. Otake, O. Hirabayashi, K. Kushida and N. Otsuka
Toshiba Corporation, Japan

11:20

11-3
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AGAND Flash Memories
Abstract   K. Otsuga, H. Kurata, K. Kozakai*, S. Noda*, Y. Sasago, T. Arigane, T. Kawamura and T. Kobayashi
Hitachi, Ltd., and *Renesas Technology Corp., Japan

11:45

11-4
A Novel Voltage Sensing 1T/2MTJ Cell with Resistance Ratio for Highly Stable and Scalable MRAM
Abstract   M. Aoki, H. Iwasa and Y. Sato
Fujitsu Laboratories LTD., Japan
back to conference schedule
(Lunch 12:10-13:50)
Friday, June 17

Session 12

High Quality Audio Chips [Shunju II]
Chairpersons M. Song, Dongguk University
P. Kinget, Columbia University

10:30

12-1
A 106dB Audio Digital-to-Analog Converter Employing Segment Flipping Technology Combined with Cascaded Dynamic Element Matching
Abstract   T. Ido, S. Ishizuka and T. Hamasaki
Texas Instruments Japan Limited, Japan

10:55

12-2
An Energy-Efficient Analog Front-End Circuit for a Sub-1V Digital Hearing Aid Chip
Abstract   S. Kim, J.-Y. Lee, S.-J. Song, N. Cho and H.-J. Yoo
KAIST, Korea

11:20

12-3
A 1-V, 1-MS/s, 88-dB Sigma-Delta Modulator in 0.13-µm Digital CMOS Technology
Abstract   L. Yao, M. Steyaert and W. Sansen
Katholieke Universiteit Leuven, Belgium

11:45

12-4
On-line Calibration and Digital Correction of Multi-bit Sigma-delta Modulators
Abstract   A. Fornasari, F. Borghetti, P. Malcovati and F. Maloberti
University of Pavia, Italy
back to conference schedule
(Lunch 12:10-13:50)
Friday, June 17

Session 13

High Speed I/O's [Shunju III]
Chairpersons K. Kobayashi, Kyoto University
W. Lee, Texas Instruments

10:30

13-1
A 3-Tap Digitally Programmable Transversal Filter in 90 nm CMOS for Equalization up to 30 Gb/s
Abstract   J. Sewter and A.C. Carusone
University of Toronto, Canada

10:55

13-2
Gain-Phase Co-Equalization for Widely-Used High- Speed Cables
Abstract   Y. Hidaka, W. Gai, H. Osone, Y. Koyanagi, J.H. Jiang and T. Horie
Fujitsu Laboratories of America, Inc., USA

11:20

13-3
A 3.125-Gb/s Sub-Milliwatt CMOS Signal Detector Circuit
Abstract   J. Savoj and P. Roo
Marvell Semiconductor, Inc., USA

11:45

13-4
A Multi-Rate 9.953-12.5GHz 0.2µm SiGe BICMOS LC Oscillator with
-120dBc/Hz Phase Noise at 1MHz Offset Using a Variable Resistor Based Varactor
Abstract   A. Maxim
Maxim Integrated Products, USA
back to conference schedule
(Lunch 12:10-13:50)
Friday, June 17

Session 14

Signal Processors [Shunju I]
Chairpersons H. Kabuo, Matsushita Electric Industrial Co., Ltd.
B. Nikolic, University of California, Berkeley

13:50

14-1
Galois Field Computation LSI: A Reconfigurable Chip for High-Speed Communication
Abstract   N. Endou, Y. Kasai*, M. Iwata*, E. Takahashi* and T. Higuchi*
ASET and *AIST, Japan

14:15

14-2
A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application
Abstract   Y. Murachi, T. Matsuno, K. Hamano, J. Miyakoshi*, M. Miyama and M. Yoshimoto*
Kanazawa University and *Kobe University, Japan

14:40

14-3
AES-Based Cryptographic and Biometric Security Coprocessor IC in 0.18-µm CMOS Resistant to Side-Channel Power Analysis Attacks
Abstract   K. Tiri, D.D. Hwang, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont and I. Verbauwhede
University of California, Los Angeles, USA

15:05

14-4
An Image Filtering Processor for Face/Object Recognition Using Merged/Mixed Analog-Digital Architecture
Abstract   K. Korekado*, T. Morie*, O. Nomura*,**, T. Nakano*, M. Matsugu**, and A. Iwata***
*Kyushu Institute of Technology, **Canon Inc. and ***Hiroshima University, Japan
back to conference schedule
(Break 15:30-15:50)
Friday, June 17

Session 15

Drivers and Sensors [Shunju II]
Chairpersons S. Sugawa, Tohoku University
H. Pon, Intel Corp.

13:50

15-1
A Low-Power Write Driver for Hard Disk Drives
Abstract   T. Kawashimo, H. Yamashita, M. Yagyu and F. Yuki
Hitachi, Ltd., Japan

14:15

15-2
A Pseudo-differential Current-mode Interface with Point-to-point Cascade Bus Architecture (WiseBus™) for Large Panel LCD Systems
Abstract   I.K. Chang, Y.W. Jeon, J.S. Lee, J.H. Hong, J.T. Kim, C.S. Choi and S. Kim*
Samsung Electronics and *Korea University, Korea

14:40

15-3
An Autonomous SRAM with On-Chip Sensors in an 80nm Double Stacked Cell Technology
Abstract   K. Sohn, N. Cho, H. Kim, K. Kim, H.-S. Mo*, Y.-H. Suh*, H.-G. Byun* and H.-J. Yoo
KAIST and *Samsung Electronics Co. Ltd., Korea

15:05

15-4
A 12-bits Resolver-to-Digital Converter Using Complex Twin PLL for Accurate Mechanical Angle Measurement
Abstract   M. Katakura, A. Toda, Y. Takagi, N. Suzuki, T. Kadoyama and H. Kushihara*
Sony Corporation and *Tamagawa Seiki Co. LTD, Japan
back to conference schedule
(Break 15:30-15:50)
Friday, June 17

Session 16

Oscillators and PLLs [Shunju III]
Chairpersons Kamei, Oki Electric Industry Co., Ltd.
B. Zhao, Skyworks Solutions

13:50

16-1
A 90-GHz Voltage-Controlled Oscillator with a 2.2- GHz Tuning Range in a 130-nm CMOS Technology
Abstract   C. Cao and K.K. O
University of Florida, USA

14:15

16-2
Fully Integrated 1.7GHz, 188dBc/Hz FoM, 0.8V, 320µW LC-tank VCO and Frequency Divider
Abstract   J. Midtgaard, T. Jeppesen, K.T. Christensen*, E. Bruun and P. Andreani
Technical University of Denmark and *Oticon A/S, Denmark

14:40

16-3
A-86dBc Reference Spurs 1-5GHz 0.13µm CMOS PLL Using a Dual-Path Sampled Loop Filter Architecture
Abstract   A. Maxim
Crystal Semiconductor, USA

15:05

16-4
A 1-V, 9.7mW CMOS Frequency Synthesizer for WLAN 802.11a Transceivers
Abstract   L.L.K. Leung and H.C. Luong
The Hong Kong University of Science and Technology, Hong Kong
back to conference schedule
(Break 15:30-15:50)
Friday, June 17

Session 17

Digital Blocks [Shunju I]
Chairpersons K. Kobayashi, Kyoto University
G. Taylor, Intel Corp.

15:50

17-1
A Self-Tuning DVS Processor Using Delay-Error Detection and Correction
Abstract   S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge and K. Flautner*
University of Michigan, USA and *ARM Inc., UK

16:15

17-2
Bitline Leakage Compensation (BLC) and Leakage Reduction (BLR) Techniques for 2-3GHz On-Chip Cache Arrays in Microprocessors on 90nm Logic Technology
Abstract   M. Khellah, Y. Ye, D. Somasekhar, D. Casper, B. Bloechel, T. Nguyen, G. Dermer, K. Zhang, G. Pandya, A. Farhang and V. De
Intel, USA

16:40

17-3
A 1.88ns 54×54-bit Multiplier in 0.18µm CMOS Based on Multiple-Valued Differential-Pair Circuitry
Abstract   A. Mochizuki and T. Hanyu
Tohoku University, Japan

17:05

17-4
A Six-Port 57GB/s Double-Pumped Nonblocking Router Core
Abstract   S. Vangal*,**, N. Borkar* and A. Alvandpour**
*Intel Corporation, USA and **Linkoping University, Sweden
back to conference schedule
(Dinner 18:00-20:00)
Friday, June 17

Session 18

Substrate Analysis and Devices [Shunju II]
Chairpersons M. Ikeda, University of Tokyo
K. Roy, Purdue University

15:50

18-1
Weak Inversion MOS Varactors for 0.5 V Analog Integrated Filters
Abstract   S. Chatterjee, T. Musah, Y. Tsividis and P. Kinget
Columbia University, USA

16:15

18-2
Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits
Abstract   D. Kosaka, M. Nagata, Y. Hiraoka*, I. Imanishi*, M. Maeda*, Y. Murasaka**, A. Iwata**
Kobe University, *Matsushita Electric Industrial Co., Ltd. and **A-R-Tec Corporation, Japan

16:40

18-3
Modeling and Experimental Verification of Substrate Coupling and Isolation Techniques in Mixed-Signal ICs on a Lightly-Doped Substrate
Abstract   G.Van der Plas*, C. Soens*,**, M. Badaroglu*, P. Wambacq*,** and S. Donnay*
*IMEC and **The Vrije Universiteit Brussel, Belgium

17:05

18-4
Feedforward Active Substrate Noise Cancelling Technique Using Power Supply di/dt Detector
Abstract   T. Nakura, M. Ikeda and K. Asada
University of Tokyo, Japan
back to conference schedule
(Dinner 18:00-20:00)
Friday, June 17

Session 19

WLAN RF ICs [Shunju III]
Chairpersons M. Ugajin, NTT Microsystem Integration Labs.
M. Huang, Freescale Semiconductor

15:50

19-1
A Fully Integrated Multi-Band MIMO WLAN Transceiver RFIC
Abstract   J.W.M. Rogers, D.G. Rahn**, M.S. Cavin**, F.F. Dai*, N. Fong**, R. Griffith**, J. Macedo**, D. Moore** and M. Toner**
Carleton University, Canada, *Auburn University, USA and **Cognio Canada, Canada

16:15

19-2
A 1.4V, 2.4/5 GHz, 90nm CMOS System in a Package Transceiver for Next Generation WLAN
Abstract   A. Ravi, B.R. Carlton, Y. Palaskas, G. Banerjee, R.E. Bishop, M.A. Elmala, R.B. Nicholls, I.A. Rippke, H. Lakdawala, L.M. Franca-Neto, S.S. Taylor and K. Soumyanath
Intel Corp., USA

16:40

19-3
A Low-IF CMOS Single-Chip Bluetooth EDR Transmitter with Digital I/Q Mismatch Trimming Circuit
Abstract   D. Miyashita, H. Ishikuro, T. Shimada, T. Tanzawa, S. Kousai, H. Kobayashi, H. Majima, K. Agawa, M. Hamada and F. Hatori
Toshiba Corporation, Japan

17:05

19-4
A Highly Linear Filter and VGA Chain with Novel DC-Offset Correction in 90nm Digital CMOS Process
Abstract   M. Elmala, B. Carlton, R. Bishop and K. Soumyanath
Intel Corporation, USA
back to conference schedule
(Dinner 18:00-20:00)
Saturday, June 18

Session 20

Low Power Design [Shunju I]
Chairpersons K. Seno, Sony Corp.
J. Farrell, AMD

8:30

20-1
The Cross Charge-Control Flip-Flop: a Low-Power and High-Speed Flip-Flop Suitable for Mobile Application SoCs
Abstract   A. Hirata, K. Nakanishi, M. Nozoe and A. Miyoshi
Matsushita Electric Industrial Co., Ltd., Japan

8:55

20-2
Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes
Abstract   M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto* and Y. Hagihara
NEC Corporation and *NEC Electronics Corporation, Japan

9:20

20-3
Optimal Zigzag (OZ): An Effective yet Feasible Power-Gating Scheme Achieving Two Orders of Magnitude Lower Standby Leakage
Abstract   K.-W. Choi, Y. Xu and T. Sakurai
University of Tokyo, Japan

9:45

20-4
Ultra-Low Voltage Power Management and Computation Methodology for Energy Harvesting Applications
Abstract   C.-Y. Tsui, H. Shao, W.-H. Ki and F. Su
The Hong Kong University of Science and Technology, Hong Kong
back to conference schedule
(Break 10:10-10:30)
Saturday, June 18

Session 21

Data Converters [Shunju II]
Chairpersons Y. Takano, Sanyo Electric Co., Ltd.
K. Nakamura, Analog Devices

8:30

21-1
A 6GS/s, 4-bit Receiver Analog-to-Digital Converter with Embedded DFE
Abstract   A. Varzaghani and C.-K.K. Yang
University of California, Los Angeles, USA

8:55

21-2
A Reconfigurable Pipelined ADC in 0.18µm CMOS
Abstract   M. Anderson, K. Norling*, A. Dreyfert* and J. Yuan
Lund University and *Wavebreaker AB, Sweden

9:20

21-3
A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s
Abstract   H. Matsui, M. Ueda, M. Daito and K. Iizuka
SHARP, Japan

9:45

21-4
A Low-Power, Low-Voltage (11mW/8.4mW, 1.2V) DAC+Filter for Multistandard (WLAN/UMTS) Transmitters
Abstract   N. Ghittori, A. Vigna, P. Malcovati, S. D'Amico* and A. Baschirotto*
University of Pavia and *University of Lecce, Italy
back to conference schedule
(Break 10:10-10:30)
Saturday, June 18

Session 22

DTV Tuner and Wireless Interconnect Techniques [Shunju III]
Chairpersons H. Yamazaki, Fujitsu Laboratories Ltd.
B. Zhao, Skyworks Solutions

8:30

22-1
A Dual-Conversion Tuner for Multi-Standard Terrestrial and Cable Reception
Abstract   I. Mehr, S. Rose, S. Nesterenko, D. Paterson, R. Schreier, H. L'Bahy, S. Kidambi, M. Elliott and S. Puckett
Analog Devices, USA

8:55

22-2
A 13 dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications
Abstract   T.W. Kim, B. Kim*, Y. Cho*, B. Kim* and K. Lee
KAIST and *Integrant Technologies, Korea

9:20

22-3
A 0.95mW/1.0Gbps Spiral-Inductor Based Wireless Chip-Interconnect with Asynchronous Communication Scheme
Abstract   M. Sasaki and A. Iwata
Hiroshima University, Japan

9:45

22-4
2.8Gb/s Inductively Coupled Interconnect for 3-D ICs
Abstract   J. Xu, J. Wilson, S. Mick, L. Luo and P. Franzon
North Carolina State University, USA
back to conference schedule
(Break 10:10-10:30)
Saturday, June 18

Session 23

Emerging DRAMs [Shunju I]
Chairpersons T. Kawahara, Hitachi Ltd.
S. Natarajan, ATMOS

10:30

23-1
An 8Mbit DRAM Design Using a 1TBulk Cell
Abstract   P. Malinge, P. Candelier, F. Jacquet, S. Martin, R. Ranica, A. Villaret, P. Mazoyer, R. Fournel and B. Allard*
STMicroelectronics and *CEGELY, INSA, France

10:55

23-2
A 0.4-V High-Speed, Long-Retention-Time DRAM Array with 12-F2 Twin Cell
Abstract   R. Takemura, K. Itoh, T. Sekiguchi, S. Akiyama, S. Hanzawa, K. Kajigaya* and T. Kawahara
Hitachi, Ltd. and *Elpida Memory, Inc., Japan

11:20

23-3
0.5V Asymmetric Three-Tr. Cell (ATC) DRAM Using 90nm Generic CMOS Logic Process
Abstract   M. Ichihashi*, H. Toda**, Y. Itoh*** and K. Ishibashi*
STARC, *Renesas Technology, **Toshiba and ***Toshiba Microelectronics, Japan

11:45

23-4
A 512Mbit, 1.6Gbps/pin DDR3 SDRAM Prototype with CIO Minimization and Self-Calibration Techniques
Abstract   C. Park, H. Chung, Y.-S. Lee, J.-K. Kim, J.-J. Lee, M.-S. Chae, D.-H. Jung, S.-H. Choi, S.-Y. Seo, T.-S. Park, J.-H. Shin, J.-H. Cho, S. Lee, K.-H. Kim, J.-B. Lee, C. Kim and S.-I. Cho
Samsung Electronics Company, Korea
back to conference schedule
(Closing 12:10)
Saturday, June 18

Session 24

Wireline Receivers and Transmitters [Shunju II]
Chairpersons M. Mizuno, NEC Corp.
A. Amerasekera, Texas Instruments

10:30

24-1
A 1-10Gbps PAM2, PAM4, PAM2 Partial Response Receiver Analog Front End with Dynamic Sampler Swapping Capability for Backplane Serial Communications
Abstract   B. Garlepp*, A. Ho*, V. Stojanovi�Lc*,**, F. Chen*, C. Werner*, G. Tsang*, T. Thrush*, A. Agarwal* and J. Zerbe*
*Rambus, Inc. and **Massachusetts Institute of Technology, USA

10:55

24-2
A 22 Gbit/s PAM-4 Receiver in 90nm CMOS-SOI Technology
Abstract   T. Toifl, C. Menolfi, M. Ruegg*, R. Reutemann*, P. Buchmann, M. Kossel, T. Morf and M. Schmatz
IBM Zurich Research Laboratory and *Miromico AG, Switzerland

11:20

24-3
A Quad 3.125Gbps Transceiver Cell with All-Digital Data Recovery Circuits
Abstract   B.-J. Lee, M.-S. Hwang, J. Kim, D.-K. Jeong and W. Kim
Seoul National University, Korea

11:45

24-4
CMOS Transmitter Using Pulse-Width Modulation Pre-Emphasis Achieving 33dB Loss Compensation at 5-Gb/s
Abstract   J.H.R. Schrader, E.A.M. Klumperink, J.L. Visschers* and B. Nauta
University of Twente and *NIKHEF, The Netherlands
back to conference schedule
(Closing 12:10)
Saturday, June 18

Session 25

Cellular RF ICs [Shunju III]
Chairpersons M. Ugajin, NTT Microsystem Integration Labs.
T. Blalock, University of Virginia

10:30

25-1
A Dual Band 1.8GHz/900MHz, 750kb/s GMSK Transmitter Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise
Abstract   S.E. Meninger and M.H. Perrott
Massachusetts Institute of Technology, USA

10:55

25-2
A Temperature Stabilized CMOS VCO for Zero-IF Cellular CDMA Receivers
Abstract   Y. Wu and V. Aparin
Qualcomm Inc., USA

11:20

25-3
A First RF Digitally-Controlled Oscillator for SAWless TX in Cellular Systems
Abstract   C.-M. Hung, N. Barton, R.B. Staszewski, M.-C. Lee and D. Leipold
Texas Instruments Inc., USA

11:45

25-4
A 0.13 um CMOS Front-End for DCS1800/UMTS/ 802.11b-g with Multi-band Positive Feedback Low Noise Amplifier
Abstract   A. Liscidini, M. Brandolini, D. Sanzogni and R. Castello
Universitá degli Studi di Pavia, Italy
back to conference schedule
(Closing 12:10)


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