Media

Media Registration

Registration for the 2024 IEEE Symposium on VLSI Technology & Circuits is complimentary for the media. Details about media registration will be available April 17, 2024.

Pre-Publication Guidelines

Prior to the start of the conference, the technical content of press releases regarding accepted papers must be limited to information included in the Symposium Advance Program or the Symposium Press Kit. After this date, press releases on the technical content of the full accepted papers are allowed.

Online Media Briefing

The Symposium organizers are planning an online briefing for the media to discuss the most newsworthy papers and major technology trends in this year’s Symposium program. Details will be available in April 2024.

Media Contacts

NORTH AMERICAN & EU
BTB Integrated Marketing –
Chris Burke, co-Media Relations Director

E-mail: chris.burke@btbmarketing.com

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JAPAN & ASIA
Secretariat for VLSI Symposia c/o JTB Communication Design, Inc. Tokyo, Japan

E-mail: vlsisymp@jtbcom.co.jp

2024 IEEE Symposium on VLSI Technology & Circuits Media Kit

Welcome to the Media Center for the Symposium. The following press materials may be downloaded for news coverage of the 2024 IEEE Symposium on VLSI Technology & Circuits.

2024 IEEE SYMPOSIUM ON VLSI TECHNOLOGY NEWS RELEASES:

2024 VLSI Call for Workshops News Release

2024 VLSI Call for Papers News Release

2024 IEEE VLSI Symposium Logo

Honolulu, Hawaii Image

Paper T1.1 An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications” – Intel Corporation (Highlight Session)

Paper T1.1 Figure 2

Paper T1.1 Figure 5

Paper T1.2 Highly Manufacturable Self-Aligned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-Dimensional Stacked FET at 48nm Gate Pitch – Samsung Electronics Co. Ltd. (Highlight Session)

Paper T1.2 Fig. 1

Paper T1.2 Fig. 4a

Paper T1.3 A Confined Storage Nitride 3D-NAND Cell with WL Airgap for Cell-to-Cell Interference Reduction and Improved Program Performances – Micron Technology Inc. (Highlight Session)

Paper T1.3 Fig. 2

Paper T1.3 Fig. 9b

Paper TFS2.3 Backside Power Distribution for Nanosheet Technologies Beyond 2nm – IBM Research

Paper TFS2.3 Fig. 5-6-7

Paper T1.4 On the Extreme Scaling of Transistors with Monolayer MoS2 Channel – TSMC (Highlight Session)

Paper T1.4 Fig. 7a-7b

Paper T1.4 Fig. 8a

Paper T9.1 Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face Architecture – Intel Corporation

Paper T9.1 Fig. 5

Paper T9.1 Fig. 10

Paper T2.1 HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C – Sony Semiconductor Solutions Corporation

Paper T2.1 Fig. 6

Paper T2.1 Fig. 9

Paper T1.5 First Demonstration of Fully Integrated 16nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory – SK Hynix Inc. (Highlight Session) 

Paper T1.5 Fig. 3b

Paper T1.5 Fig. 9

Paper T4.1 Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal Gate Towards Vertical Logic and Memory – Purdue University

Paper T4.1 Fig. 12

Paper T4.1 Fig. 17a

Paper T4.1 Fig. 17b

Paper T17.2 4F2 Stackable Polysilicon Channel Access Device for Ultra-Dense NVDRAM – Micron Technology Inc.

Paper T17.2 Fig. 1

Paper T17.2 Fig. 8a

Paper T5.4 Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5) – imec

Paper T5.4 Fig. 14

Paper T5.4 Fig. 16

Paper C7.4 Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET – ETH Zürich, Stanford University, and University of Bologna

Paper C7.4 Fig. 1

Paper C7.4 Fig. 2

Paper C20.1 Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow – KAIST and Samsung Electronics

Paper C20.1 Fig. 2

Paper C16.3 A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology – Arm

Paper C16.3 Fig. 2a

Paper C25.1 A 5.6μW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy – Seoul National University and Columbia University

Paper C25.1 Fig. 2

Paper C25.1 Fig. 4

Paper C23.1 SPIRIT: A Seizure Prediction SoC with a 17.2nJ/cls Unsupervised Online-Learning Classifier and Zoom Analog Frontends – University of California, Berkeley

Paper C23.1 Fig. 1

Paper C23.1 Fig. X

Paper C6.1 3D-Stacked 1Megapixel Time-Gated SPAD Image Sensor with 2D Interactive Gating Network for Image Alignment-Free Sensor Fusion – Canon Inc.

Paper C6.1 Fig. 1

Paper C6.1 Fig. 6

Paper C24.2 A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS – University of Southern California and MediaTek

Paper C24.2 Fig. 3

Paper C5.3 A 5.8W, 0.00086% THD+N, 118dB PSRR Class-D Audio Amplifier with Passive Output Common-Mode Compensation Technique for Wide Output Power Range – Samsung Electronics

Paper C5.3 Fig. 1

Paper C5.3 Fig. 7

Paper C14.1 A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4 – TSMC

Paper C14.1 Fig. 4

Paper C14.1 Fig. 6b

Paper C14.4 A 4x50Gb/s NRZ 1.5pJ/b Co-Packaged and Fiber-Terminated 4-Channel Optical RX – Intel Corporation

Paper C14.4 Fig. 1

Paper C9.2 A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset – Tokyo Institute of Technology

Paper C9.2 Fig. 1