2005 SYMPOSIUM ON VLSI TECHNOLOGY

Welcome to the 2007 Symposium on VLSI Technology

On behalf of the Organizing Committee, it is our great pleasure to invite you to the 2007 Symposium on VLSI Technology which will be held from June 12-14 in Kyoto, Japan. This symposium has been recognized as one of the premiere technical conferences on the latest
research and developments in the field of VLSI technologies and their applications, and this year is no exception.

The Program Committee of this year has selected 86 top quality papers addressing a wide range of topics from 218 submitted papers, and has organized 21 technical sessions for the Kyoto symposium. We are also delighted to have two very distinguished invited speakers for the plenary session. Toshimi Abo of Nissan Motor Co., Ltd. will present a talk on “Future Vehicle Technologies for Environment and Safety” and Cary Gunn of Luxtera, Inc. will give a talk on “Fully Integrated VLSI CMOS and Photonics” as the advanced and exciting technologies and their applications.

Furthermore, this year we introduce a new session, called “Focus Session” in the morning of June 13. In this session, DFM/DFY technologies, which is presently one of the most important and critical issues, will be presented and discussed by excellent invited speakers. They are Hidetoshi Onodera of Kyoto University, Asen Asenov of University of Glasgow, Michihiro Kanno of Sony Corporation, Mark Mason of Texas Instruments, Inc.

Three Rump Sessions are planned for the evening of June 13 as a means to facilitate informal discussion among attendees. Two of the Rump Sessions are regular sessions covering specific technology related topics of timely interest:
1. Navigating the Roadmap to 32nm and Beyond: Breaking the Barriers.
2. The Status and Prognosis for High-k/Metal-Gate Transistors.
The third is a joint Session with the Symposium on VLSI Circuits. It will focus on the variability issue with the title “Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?”

A one-day Short Course, scheduled for June 11, will cover “Outlook for 32nm CMOS Logic and Memory Technologies”. This should be an excellent opportunity for experienced as well as new engineers to broaden their technical base. The symposium registration fee covers all of the sessions including the Rump Sessions, the symposium proceedings, the symposium banquet, and a DVD containing all of the contents of the Digests from the past 27 years as the 20th anniversary gift of the VLSI Circuits Symposium. Registration for the Short Course includes the attendance to the short course as well as a booklet containing the short course presentation materials. The detailed registration fees and hotel reservation schedules are included in the Advance Program.

We look forward to seeing you at this very exciting symposium in beautiful Kyoto and we are sure that you will find the conference exciting and rewarding.


Tohru Mogami

Charles Dennison
Program Chair Program Co-Chair




CONFERENCE SCHEDULE


Sunday, June 10

8:00-17:00

Registration
Monday, June 11 7:00 Breakfast
8:00 Registration
8:55-12:15 Short Course [Shunju]
13:45-17:00 Short Course [Shunju]
18:00-20:00 Reception [Suzaku]
Tuesday, June 12 7:00 Breakfast
8:00 Registration
8:30-10:15 Session 1 Welcome and Plenary Session [Shunju]
10:30-12:10 Session 2 Highlights [Shunju]
13:30-15:10 Session 3A Variability in SRAM [Shunju]
Session 3B Gate Dielectric Reliability and Solid-Electrode Switch [Suzaku]
15:25-17:30 Session 4A Strained Silicon Technology [Shunju]
Session 4B Analog/RF/Mixed-Signal VLSI and CMOS Image Sensor [Suzaku]
19:00-21:00 Dinner [Shunju]
Wednesday, June 13 7:00 Breakfast
8:30-10:10 Session 5A High-K/Metal Gate Stacks [Shunju I]
Session 5B Advanced SRAM Technology [Shunju II]
10:30-12:10 Session 6A Focus Session: DFM/DFY Technologies [Shunju I]
Session 6B Advanced Nonvolatile Memory I [Shunju II]
13:30-15:10 Session 7A Multi-Gate FETs [Shunju I]
Session 7B Source/Drain Engineering [Shunju II]
15:25-17:30 Session 8A Mobility Enhancement and Characterization [Shunju I]
Session 8B Nonvolatile Trapped Charge Memory [Shunju II]
20:00-22:00 Rump Sessions [Suzaku, Shunju]
Thursday, June 14 7:00 Breakfast
8:30-10:10 Session 9A Metal/FUSI Devices [Shunju I]
Session 9B Novel DRAM Technology I [Shunju II]
10:30-12:10 Session 10A CMOS Platform/Integration Technology [Shunju I]
Session 10B Novel DRAM Technology II [Shunju II]
13:30-15:10 Session 11A Metal Gate CMOS [Shunju I]
Session 11B Variability in CMOS [Shunju II]
15:25-17:30 Session 12A Advanced CMOS Devices [Shunju I]
Session 12B Advanced Nonvolatile Memory II [Shunju II]




PROGRAM

Tuesday, June 12

Session 1

Welcome and Plenary Session [Shunju]
Chairpersons T. Mogami, Semiconductor Leading Edge Technologies, Inc.
C. Dennison, Ovonyx, Inc.

8:30

1-1
Welcome and Opening Remarks
   S. Kimura, Hitachi, Ltd.
J. Woo, Univ. of California, Los Angeles

8:55

1-2
Future Vehicle Technologies for Environment and Safety
Invited T. Abo, Nissan Motor Co., Ltd.

9:35

1-3
Fully Integrated VLSI CMOS and Photonics
Invited C. Gunn, Luxtera, Inc.
back to conference schedule
(Break 10:15-10:30)
Tuesday, June 12

Session 2

Highlights [Shunju]
Chairpersons S.S. Chung, National Chiao Tung University
M.-R. Lin, AMD

10:30

2-1
Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory
abstract D. Kwak, J. Park, K. Kim, Y. Yim, S. Ahn, Y. Park, J. Kim, W. Jeong, J. Kim, M. Park, B. Yoo, S. Song, H. Kim, J. Sim, S. Kwon, B. Hwang, H. Park, S. Kim, Y. Lee, H. Shin, N. Yim, K. Lee, M. Kim, Y. Lee, J. Park, S. Park, J. Jung and K. Kim
Samsung Electronics Co., LTD, Korea

10:55

2-2
Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory
abstract H. Tanaka, M. Kido, K. Yahashi*, M. Oomura*, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata**, Y. Matsuoka, Y. Iwata, H. Aochi and A. Nitayama
TOSHIBA Corporation, *Center for Semiconductor Research & Development and Process & Manufacturing Engineering Center Toshiba Corporation, Semiconductor Company and **Toshiba Information Systems (Japan) Corporation, Japan

11:20

2-3
High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology
abstract Z. Luo, N. Rovedo, S. Ong*, B. Phoong*, M. Eller**, H. Utomo, C. Ryou***, H. Wang, R. Stierstorfer**, L. Clevenger, S. Kim, J. Toomey, D. Sciacca, J. Li, W. Wille, L. Zhao*, L. Teo*, T. Dyer, S. Fang, J. Yan**, O. Kwon, O. Kwon**, D. Park, J. Holt, J. Han**, V. Chan, J. Yuan, T. Kebede, H. Lee, S. Kim**, S. Lee***, A. Vayshenker, Z. Yang, C. Tian, H. Ng, H. Shang, M. Hierlemann**, J. Ku***, J. Sudijono* and M. Ieong
IBM Semiconductor Research and Development Center (SRDC), *Chartered Semiconductor Manufacturing, **Infineon Technologies AG and***Samsung Electronics Co., Ltd, USA

11:45

2-4
Low Vt Ni-FUSI CMOS Technology Using a DyO Cap Layer with Either Single or Dual Ni-phases
abstract H.Y. Yu, S.Z. Chang*, A. Veloso, A. Lauwers, C. Adelmann, B. Onsia, S. Van Elshocht, R. Singanamalla, M. Demand, R. Vos, T. Kauerauf, S. Brus, X. Shi, S. Kubicek, C. Vrancken, R. Mitsuhashi**, P. Lehnen****, J. Kittl***, M. Niwa**, K.M. Yin*****, T. Hoffmann, S. Degendt, M. Jurczak, P. Absil and S. Biesemans
IMEC, *TSMC, **Matsushita, ***Texas Instruments, ****Aixtron assignee to IMEC and *****TSMC, Belgium
back to conference schedule
(Lunch 12:10-13:30)
Tuesday, June 12

Session 3A

Variability in SRAM [Shunju]
Chairpersons T. Hiramoto, University of Tokyo
T. Skotnicki, STMicroelectronics

13:30

3A-1
SRAM Critical Yield Evaluation Based on Comprehensive Physical / Statistical Modeling, Considering Anomalous Non-Gaussian Intrinsic Transistor Fluctuations
abstract M. Miyamura, T. Fukai*, T. Ikezawa**, R. Ueno**, K. Takeuchi and M. Hane
NEC Corporation, *NEC Electronics Corporation and **NEC Informatec Systems, Japan

13:55

3A-2
Impact of Layout, Interconnects and Variability on CMOS Technology Roadmap
abstract F. Boeuf, M. Sellier, A. Farcy and T. Skotnicki
STMicroelectronics, France

14:20

3A-3
1st Quantitative Failure-Rate Calculation for The Actual Large-Scale SRAM Using Ultra-Thin Gate-Dielectric with Measured Probability of The Gate-Current Fluctuation and Simulated Circuit Failure-Rate
abstract T. Sakoda, N. Tamura, S. Xiao, H. Minakata, Y. Morisaki, K. Nishigaya, T. Saiki*, T. Uetake*, T. Iwasaki*, H. Ehara*, H. Matsuyama*, H. Shimizu*, K. Hashimoto*, M. Kimoto*, M. Kase* and K. Ikeda
Fujitsu Laboratories Ltd. and *Fujitsu Ltd., Japan

14:45

3A-4
Layout-Design Methodology of 0.246-μm2 -Embedded 6T-SRAM for 45-nm High-Performance System LSIs
abstract R. Morimoto, T. Kimura*, Y. Okayama*, T. Hirai***, H. Maeda, K. Oshima, R. Watanabe*, H. Fukui*, Y. Tsunoda*, M. Togo***, S. Kanai, S. Shino, T. Hoshino**, K. Shimazaki**, M. Nakazawa, K. Nakazawa, Y. Takasu*, H. Yamasaki*, H. Inokuma*, S. Taniguchi*, T. Fujimaki*, H. Yamada*, S. Watanabe***, S. Muramatsu***, S. Iwasa*, K. Nagaoka, S. Mimotogi*, T. Iwamoto***, H. Nii*, Y. Sogo, K. Ohno, K. Yoshida*, K. Sunouchi*, M. Ikeda***, M. Iwai*, T. Kitano***, H. Naruse*, Y. Enomoto, K. Imai***, S. Yamada*, M. Saito, T. Kuwata***, F. Matsuoka* and N. Nagashima
Sony Corporation, *Toshiba Corporation, **Toshiba Microelectronics Corporation and ***NEC Electronics Corporation, Japan
back to conference schedule
(Break 15:10-15:25)
Tuesday, June 12

Session 3B

Gate Dielectric Reliability and Solid-Electrode Switch [Suzaku]
Chairpersons C.C. Wu, TSMC
M. Mirabedini, Silicon Integrated Solutions

13:30

3B-1
Advanced Electrical Characterization Toward (Sub) 1nm EOT HfSiON − Hole Trapping in PFET and L-Dependent Effects
abstract M.B. Zahid*,**, L. Pantisano*, R. Degraeve*, M. Aoulaiche*,****, L. Trojman*,****, I. Ferain*,****, E.S. Andrés***, G. Groeseneken*,****, J.F. Zhang**, M. Heyns*,****, M. Jurczak* and S. De Gendt*,*****
*IMEC, Belgium, **JMU Liverpool, UK, ***UCM Madrid, Spain, ****ESAT, Belgium and *****Chemistry dept., Belgium

13:55

3B-2
Reliability Perspective of High-k Gate Stack Assessed by Temperature Dependence of Dielectric Breakdown
abstract K. Okada, T. Horikawa*, H. Satake, S. Inumiya**, Y. Akasaka**, F. Ootsuka**, Y. Nara**, H. Ota*, T. Nabatame and A. Toriumi*,***
MIRAI-ASET, *MIRAI-ASRC, AIST, **Semiconductor Leading Edge Technologies (Selete) and ***The University of Tokyo, Japan

14:20

3B-3
Physical Understanding of Strain Effects on Gate Oxide Reliability of MOSFETs
abstract T. Irisawa*, T. Numata*, E. Toyoda***, N. Hirashita, T. Tezuka, N. Sugiyama* and S. Takagi**
*MIRAI-ASET, **MIRAI-AIST and ***Toshiba Ceramics, Japan

14:45

3B-4
A Ta2O5 Solid-Electrolyte Switch with Improved Reliability
abstract T. Sakamoto*,**, N. Banno*,**, N. Iguchi*, H. Kawaura*, H. Sunamura*, S. Fujieda*, K. Terabe**,***, T. Hasegawa**,*** and M. Aono**,***
*NEC Corp., **ICORP, Japan Science & Technology Agency (JST) and ***National Institute of Material Science, Japan
back to conference schedule
(Break 15:10-15:25)
Tuesday, June 12

Session 4A

Strained Silicon Technology [Shunju]
Chairpersons T. Yamashita, Renesas Technology Corp.
F. Nouri, Applied Materials, Inc.

15:25

4A-1
Beneath-The-Channel Strain-Transfer-Structure (STS) and Embedded Source/Drain Stressors for Strain and Performance Enhancement of Nanoscale MOSFETs
abstract K.-W. Ang, J. Lin, C.-H. Tung*, N. Balasubramanian*, G. Samudra and Y.-C. Yeo
National University of Singapore and *Institute of Microelectronics, Singapore

15:50

4A-2
Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy
abstract Y. Liu, O. Gluschenkov, J. Li, A. Madan, A. Ozcan, B. Kim, T. Dyer, A. Chakravarti, K. Chan*, C. Lavoie*, I. Popova, T. Pinto, N. Rovedo, Z. Luo, R. Loesing, W. Henson and K. Rim
IBM Semiconductor Research and Development Center (SRDC) and *IBM T. J. Watson Research Center, USA

16:15

4A-3
Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process
abstract J. Wang, Y. Tateshita, S. Yamakawa, K. Nagano, T. Hirano, Y. Kikuchi, Y. Miyanami, S. Yamaguchi, K. Tai, R. Yamamoto, S. Kanda, T. Kimura, K. Kugimiya, M. Tsukamoto, H. Wakabayashi, Y. Tagawa, H. Iwamoto, T. Ohno, M. Saito, S. Kadomura and N. Nagashima
SONY Corporation, Japan

16:40

4A-4
Record-High Performance 32 nm Node pMOSFET with Advanced Two-Step Recessed SiGe-S/D and Stress Liner Technology
abstract N. Yasutake, A. Azuma, T. Ishida, N. Kusunoki*, S. Mori**, H. Itokawa**, I. Mizushima**, S. Okamoto* T. Morooka, N. Aoki, S. Kawanaka, S. Inaba and Y. Toyoshima
Toshiba Corporation Semiconductor Company, *System LSI Division and **Process & Manufacturing Engineering Center, Japan

17:05

4A-5
Impact of Mobility Boosters (XsSOI, CESL, TiN Gate) on the Performance of ‹100› or ‹100› Oriented FDSOI cMOSFETs for the 32nm Node
abstract F. Andrieu, O. Faynot, F. Rochette*, J.-C. Barbé, C. Buj, Y. Bogumilowicz, F. Allain, V. Delaye, D. Lafond, F. Aussenac, S. Feruglio*, J. Eymery, T. Akatsu***, P. Maury**, L. Brévard, L. Tosti, H. Dansas, E. Rouchouze**, J.-M. Hartmann, L. Vandroux, M. Cassé, F. Boeuf**, C. Fenouillet-Béranger, F. Brunier***, I. Cayrefourcq***, C. Mazuré***, G. Ghibaudo* and S. Deleonibus
CEA LETI-MINATEC, *IMEP-MINATEC, **STMicroelectronics and ***SOITEC, France
back to conference schedule
(Dinner: 19:00-21:00 [Shunju])
Tuesday, June 12

Session 4B

Analog / RF / Mixed-Signal VLSI and CMOS Image Sensor [Suzaku]
Chairpersons H. Matsuhashi, Oki Electric Industry Co., Ltd.
C. Bulucea, National Semiconductor Corp.

15:25

4B-1
SOI CMOS Technology with 360GHz fT NFET, 260GHz fT PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog Systemon-Chip Applications
abstract S. Lee, J. Kim, D. Kim, B. Jagannathan, C. Cho, J. Johnson, B. Dufrene, N. Zamdmer, L. Wagner, R. Williams, D. Fried, K. Rim, J. Pekarik, S. Springer, J.-O. Plouchart and G. Freeman
IBM Semiconductor Research and Development Center, USA

15:50

4B-2
Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process
abstract H. Li, B. Jagannathan*, J. Wang*, T.-C. Su*, S. Sweeney, J.J. Pekarik, Y. Shi, D. Greenberg*, Z. Jin, R. Groves*, L. Wagner* and S. Csutak
IBM System and Technology Group, Burlington, VT and *Hopewell Junction, USA

16:15

4B-3
Reliable 3D Damascene MIM Architecture Embedded into Cu Interconnect for a Ta2O5 Capacitor Record Density of 17 fF/μm2
abstract M. Thomas*,**, A. Farcy*, C. Perrot*, E. Deloffre*, M. Gros-Jean*, D. Benoit*, C. Richard*, P. Caubet*, S. Guillaumet*, R. Pantel*, M. Cordeau***, J. Piquet****, C. Bermond****, B. Fléchet****, B. Chenevier** and J. Torres*
*STMicroelectronics, **LMGP, ***CEA-LETI and ****LAHC, France

16:40

4B-4
BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design
abstract M.V. Dunga*, C.-H. Lin*, D.D. Lu*, W. Xiong**, C.R. Cleavelin**, P. Patruno***, J.-R. Hwang****, F.-L. Yang****, A.M. Niknejad* and C. Hu*
*University of California, Berkeley, **Texas Instruments Inc., USA, ***SOITECH S.A., France and ****Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan

17:05

4B-5
Dedicated Process Architecture and the Characteristics of 1.4 μm Pixel CMOS Image Sensor with 8M Density
abstract C.-R. Moon, J.-C. Shin, J. Kim, Y.K. Lee, Y.-J. Cho, Y.-Y. Yu, S.-H. Hwang, D.-C. Park, B.J. Park, H.-Y. Kim, S.-H. Lee, J. Jung*, S.-H. Cho, K. Lee, K. Koh, D. Lee and K. Kim
Samsung Electronics Co. and *Sejong University, Korea
back to conference schedule
(Dinner: 19:00-21:00 [Shunju])
Wednesday, June 13

Session 5A

High-K / Metal Gate Stacks [Shunju I]
Chairpersons M. Niwa, Semiconductor Company, Matsushita Electric Ind., Co., Ltd.
S. Biesemans, IMEC

8:30

5A-1
Fermi-Level Pinning Position Modulation by Al- Containing Metal Gate for Cost-Effective Dual- Metal/Dual-High-k CMOS
abstract M. Kadoshima*, Y. Sugita*, K. Shiraishi**, H. Watanabe***, A. Ohta****, S. Miyazaki****, K. Nakajima*****, T. Chikyow*****, K. Yamada******, T. Aminaka*, E. Kurosawa*, T. Matsuki*, T. Aoyama*, Y. Nara* and Y. Ohji*
*Semiconductor Leading Edge Technologies Inc. (Selete), **University of Tsukuba, ***Osaka University, ****Hiroshima University, *****National Institute for Material Science and ******Waseda University, Japan

8:55

5A-2
Dipole Moment Model Explaining nFET Vt Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics
abstract P. Sivasubramani, T.S. Böscke*, J. Huang, C.D. Young, P.D. Kirsch**, S.A. Krishnan, M.A. Quevedo-Lopez***, S. Govindarajan*, B.S. Ju, H.R. Harris****, D.J. Lichtenwalner*****, J.S. Jur*****, A.I. Kingon*****, J. Kim******, B.E. Gnade******, R.M. Wallace******, G. Bersuker, B.H. Lee** and R. Jammy**
SEMATECH, *Qimonda, **IBM, ***TI, ****AMD, *****North Carolina State University and ******University of Texas at Dallas, USA

9:20

5A-3
Re-examination of Flat-Band Voltage Shift for High-k MOS Devices
abstract K. Iwamoto*, A. Ogawa*, Y. Kamimuta*, Y. Watanabe*, W. Mizubayashi**, S. Migita**, Y. Morita**, M. Takahashi*, H. Ito*, H. Ota**, T. Nabatame* and A. Toriumi**,***
*MIRAI-ASET, **MIRAI-ASRC and ***The University of Tokyo, Japan

9:45

5A-4
VFB Roll-off in HfO2 Gate Stack after High Temperature Annealing Process
- A Crucial Role of Out-diffused Oxygen from HfO2 to Si -
abstract K. Akiyama*, W. Wang**, W. Mizubayashi**, M. Ikeda*, H. Ota**, T. Nabatame* and A. Toriumi**,***
*MIRAI-ASET, **MIRAI-ASRC and ***The University of Tokyo, Japan
back to conference schedule
(Break 10:10-10:30)
Wednesday, June 13

Session 5B

Advanced SRAM Technology [Shunju II]
Chairpersons J. H. Lee, MagnaChip Semiconductor Ltd.
T. Grider, Texas Instruments

8:30

5B-1
0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node
abstract H. Onoda, K. Miyashita, T. Nakayama, T. Kinoshita, H. Nishimura*, A. Azuma**, S. Yamada and F. Matsuoka
Semiconductor Company, Toshiba Corporation, *Process and Manufacturing Engineering Center and **Center for Semiconductor R&D, Japan

8:55

5B-2
A Robust SOI SRAM Architecture by Using Advanced ABC Technology for 32nm Node and Beyond LSTP Devices
abstract Y. Hirano, M. Tsujiuchi, K. Ishikawa*, H. Shinohara, T. Terada, Y. Maki, T. Iwamatsu, K. Eikyu, T. Uchida, S. Obayashi, K. Nii, Y. Tsukamoto, M. Yabuuchi, T. Ipposhi, H. Oda and Y. Inoue
Renesas Technology Corp. and *Renesas Semiconductor Engineering, Japan

9:20

5B-3
Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
abstract Y.-H. Son, J.-W. Lee, P. Kang, M.-G. Kang, J.B. Kim, S.H. Lee, Y.-P. Kim, I.S. Jung, B.C. Lee, S.Y. Choi, U.I. Chung, J.T. Moon and B.-I. Ryu
Samsung Electronics Co., Ltd., Korea

9:45

5B-4
High Speed and Highly Cost effective 72M bit density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory
abstract S.-M. Jung, H. Lim, C. Yeo, K. Kwak, B. Son, H. Park, J. Na, J.-J. Shim, C. Hong and K. Kim
Samsung Electronics, Korea
back to conference schedule
(Break 10:10-10:30)
Wednesday, June 13

Session 6A

Focus Session: DFM / DFY Technologies [Shunju I]
Chairpersons H. Wakabayashi, Sony Corp.
C. Dennison, Ovonyx, Inc.

10:30

6A-1
Simulation of Statistical Variability in Nano MOSFETs
  A. Asenov
The University of Glasgow, UK

10:55

6A-2
Empirical Characteristics and Extraction of Overall Variations for 65-nm MOSFETs and Beyond
  M. Kanno, A. Shibuya, M. Matsumura, K. Tamura, H. Tsuno, S. Mori, Y. Fukuzaki, T. Gocho, H. Ansai and N. Nagashima
Sony Corporation, Japan

11:20

6A-3
DFM EDA Technology: A Lithographic Perspective
  M.E. Mason
Texas Instruments Incorporated, USA

11:45

6A-4
Toward Variability-Aware Design
  H. Onodera
Kyoto University, Japan
back to conference schedule
(Lunch 12:10-13:30)
Wednesday, June 13

Session 6B

Advanced Nonvolatile Memory I [Shunju II]
Chairpersons T. Nakamura, Rohm Co., Ltd.
A. Lacaita, Politecnico di Milano

10:30

6B-1
Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)
abstract D.H. Kang, J.S. Kim, Y.R. Kim, Y.T. Kim, M.K. Lee, Y.J. Jun, J.H. Park, F. Yeung, C.W. Jeong, J. Yu, J.H. Kong, D.W. Ha, S.A. Song*, J. Park*, Y.H. Park, Y.J. Song, C.Y. Eum, K.C. Ryoo, J.M. Shin, D.W. Lim, S.S. Park, J.H. Kim, W.I. Park, K.R. Sim, J.H. Cheong, J.H. Oh, J.H. Park, J.I. Kim, Y.T. Oh, K.W. Lee, S.P. Koh, S.H. Eun, N.B. Kim, G.H. Koh, G.T. Jeong, H.S. Jeong and K. Kim
Samsung Electronic Co., Ltd. and *Samsung Advanced Institute of Technology, Korea

10:55

6B-2
An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory
abstract Y. Zhang, S.B. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi and H.-S.P. Wong
Stanford University, USA

11:20

6B-3
Novel Lithography-Independent Pore Phase Change Memory
abstract M. Breitwisch, T. Nirschl*, C.F. Chen***, Y. Zhu, M.H. Lee, M. Lamorey****, G.W. Burr******, E. Joseph, A. Schrott, J.B. Philipp**, R. Cheek, T.D. Happ**, S.H. Chen***, S. Zaidi**, P. Flaitz*****, J. Bruley*****, R. Dasaka, B. Rajendran, S. Rossnagel, M. Yang, Y.C. Chen***, R. Bergmann**, H.L. Lung*** and C. Lam
IBM T.J. Watson Research Center, *Infineon Technologies, **Qimonda, ***Macronix, ****IBM Essex Junction, *****IBM Fishkill, ******IBM Almaden Research Center, USA

11:45

6B-4
Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation
abstract J.I. Lee, H. Park, S.L. Cho, Y.L. Park, B.J. Bae, J.H. Park, J.S. Park, H.G. An, J.S. Bae, D.H. Ahn, Y.T. Kim, H. Horii, S.A. Song*, J.C. Shin, S.O. Park, H.S. Kim, U.-I. Chung, J.T. Moon and B.I. Ryu
Samsung Electronics Co., Ltd. and *Samsung Advanced Institute of Technology, Korea
back to conference schedule
(Lunch 12:10-13:30)
Wednesday, June 13

Session 7A

Multi-Gate FETs [Shunju I]
Chairpersons M. Masahara, National Institute of Advanced Industrial Science and Technology (AIST)
T.J. King Liu, Univ. of California

13:30

7A-1
A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
abstract K. von Arnim, E. Augendre**, C. Pacha*, T. Schulz, K.T. San**,***, F. Bauer*, A. Nackaerts**, R. Rooyackers**, T. Vandeweyer**, B. Degroote**, N. Collaert**, A. Dixit**, R. Singanamalla**, W. Xiong***, A. Marshall***, C.R. Cleavelin***, K. Schrüfer* and M. Jurczak**
Infineon Technologies Leuven, Belgium, *Infineon Technologies, Germany, **IMEC, Belgium and ***Texas Instruments, USA

13:55

7A-2
Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated Source/Drain N-channel MuGFETs
abstract R.T.P. Lee, T.-Y. Liow, K.-M. Tan, A.E.-J. Lim, C.-S. Ho***, K.-M. Hoe**, M.Y. Lai*, T. Osipowicz***, G.-Q. Lo**, G. Samudra, D.-Z. Chi* and Y.-C. Yeo
National University of Singapore, *Institute of Materials Research and Engineering, **Institute of Microelectronics and ***National University of Singapore, Singapore

14:20

7A-3
Highly Manufacturable FinFETs with Sub-10nm Fin Width and High Aspect Ratio Fabricated with Immersion Lithography
abstract M.J.H.van Dal, N. Collaert*, G. Doornbos, G. Vellianitis, G. Curatola, B.J. Pawlak, R. Duffy, C. Jonville, B. Degroote*, E. Altamirano*, E. Kunnen*, M. Demand*, S. Beckx*, T. Vandeweyer*, C. Delvaux*, F. Leys*, A. Hikavyy*, R. Rooyackers*, M. Kaiser**, R.G.R. Weemaes**, S. Biesemans*, M. Jurczak*, K. Anil*, L. Witters* and R.J.P. Lander
NXP Semiconductors, *IMEC, Belgium and **Philips Research Europe, The Netherlands

14:45

7A-4
Novel, Effective and Cost-Efficient Method of Introducing Fluorine into Metal/Hf-based Gate Stack in MuGFET and Planar SOI Devices with Significant BTI Improvement
abstract A. Shickova*,**, N. Collaert*, P. Zimmerman***, M. Demand*, E. Simoen*, G. Pourtois*, A. De Keersgieter*, L. Trojman*,**, I. Ferain*,**, F. Leys*, W. Boullart*, A. Franquet*, B. Kaczer*, M. Jurczak*, H. Maes*,** and G. Groeseneken*,*
*IMEC, **K.U.Leuven and ***Intel Corporation, Belgium
back to conference schedule
(Break 15:10-15:25)
Wednesday, June 13

Session 7B

Source / Drain Engineering [Shunju II]
Chairpersons Y. Tada, Tokyo Electron Ltd.
J. Hutchby, SRC

13:30

7B-1
Technology Breakthrough of Low Temperature, Low Defect, and Low Cost SiGe Selective Epitaxial Growth (L3 SiGe SEG) Process for 45nm Node and Beyond
abstract Y. Shimamune, M. Fukuda*, M. Koiizuka*, A. Katakami, A. Hatada, K. Ikeda, Y. Kim, K. Kawamura*, N. Tamura, T. Mori*, A. Moriya**, Y. Hashiba**, Y. Inokuchi**, Y. Kunii** and M. Kase*
Fujitsu Laboratories Ltd., *Fujitsu Ltd. and **Hitachi Kokusai Electric Inc., Japan

13:55

7B-2
Enhanced Performance of Strained CMOSFETs Using Metallized Source/Drain Extension (M-SDE)
abstract H.-W. Chen, C.-H. Ko, T.-J. Wang, C.-H. Ge, K. Wu and W.-C. Lee
Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan, ROC

14:20

7B-3
Novel Thin Sidewall Structure for High Performance Bulk CMOS with Charge-Assisted Source-Drain-Extension
abstract H. Ohta, H. Fukutome, T. Sakuma, A. Hatada, K. Ohkoshi*, K. Ikeda, T. Miyashita, T. Mori* and T. Sugii
Fujitsu Laboratories Ltd. and *Fujitsu Limited, Japan

14:45

7B-4
Advantages of a New Scheme of Junction Profile Engineering with Laser Spike Annealing and Its Integration into a 45-nm Node High Performance CMOS Technology
abstract T. Yamamoto, T. Kubo*, T. Sukegawa*, A. Katakami, Y. Shimamune, N. Tamura, H. Ohta, T. Miyashita, S. Sato, M. Kase* and T. Sugii
Fujitsu Laboratories Ltd. and *Fujitsu Ltd., Japan
back to conference schedule
(Break 15:10-15:25)
Wednesday, June 13

Session 8A

Mobility Enhancement and Characterization [Shunju I]
Chairpersons T. Yamashita, Renesas Technology Corp.
K. Schruefer, Infineon Technologies AG

15:25

8A-1
Stress Dependence and Poly-Pitch Scaling Characteristics of (110) PMOS Drive Current
abstract B.(F) Yang, K. Nummy*, A. Waite, L. Black, H. Gossmann, H. Yin*, Y. Liu*, B. Kim*, S. Narasimha*, P. Fisher, H.V. Meer, J. Johnson*, D. Chidambarrao*, S.D. Kim*, C. Sheraw*,
D. Wehella-Gamage*, J. Holt*, X. Chen*, D. Park*, C.Y. Sung*, D. Schepis*, M. Khare*, S. Luning and P. Agnello*
Advanced Micro Devices and *IBM Systems and Technology Group, USA

15:50

8A-2
Will Strain be Useful for 10nm Quasi-Ballistic FDSOI Devices? An Experimental Study
abstract V. Barral*,**, T. Poiroux*, F. Rochette*, M. Vinet*, S. Barraud*, O. Faynot*, L. Tosti*, F. Andrieu*, M. Cassé*, B. Prévitali*, R. Ritzenthaler*, P. Grosgeorges*, E. Bernard*, G. LeCarval*, D. Munteanu**, J.L. Autran** and S. Deleonibus*
*CEA/LETI MINATEC and **L2MP, France

16:15

8A-3
New Findings on Coulomb Scattering Mobility in Strained-Si nFETs and its Physical Understanding
abstract O. Weber and S. Takagi
The University of Tokyo, Japan

16:40

8A-4
Stress Engineering for High-k FETs: Mobility and Ion Enhancements by Optimized Stress
abstract M. Saitoh, S. Kobayashi and K. Uchida
Toshiba Corporation, Japan

17:05

8A-5
High-Field Electron Mobility in Biaxially-tensile Strained SOI: Low Temperature Measurement and Correlation with the Surface Morphology
abstract O. Bonno, S. Barraud, F. Andrieu, D. Mariolle, F. Rochette*, M. Cassé, J.M. Hartmann, F. Bertin and O. Faynot
CEA/LETI Minatec and *IMEP, France
back to conference schedule
Wednesday, June 13

Session 8B

Nonvolatile Trapped Charge Memory [Shunju II]
Chairpersons R. Yamada, Hitachi Ltd.
K.-M. Chang, Freescale

15:25

8B-1
Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory
abstract Z.L. Huo, J. Yang, S.H. Lim, S.J. Baik, J. Lee, J.H. Han, I.-S. Yeo, U.-I. Chung, J.T. Moon and B.-I. Ryu
Samsung Electronics Co., LTD., Korea

15:50

8B-2
A Novel Gate-Injection Program/Erase P-Channel NAND-Type Flash Memory with High (10M Cycle) Endurance
abstract H.-T. Lue, E.-K. Lai, S.-Y. Wang, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu and C.-Y. Lu
Macronix International Co. Ltd, Taiwan

16:15

8B-3
Gate-All-Around Twin Silicon Nanowire SONOS Memory
abstract S.D. Suk, K.H. Yeo, K.H. Cho, M. Li, Y.Y. Yeoh, K.-H. Hong, S.-H. Kim, Y.-H. Koh, S. Jung, W.J. Jang, D.-W. Kim, D. Park and B.-I. Ryu
Samsung Electronics Co., Korea

16:40

8B-4
A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices
abstract H. Lee, S.-W. Ryu, J.-W. Han, L.-E. Yu, M. Im, C. Kim, S. Kim, E. Lee, K.-H. Kim, J.-H. Kim, D.-i. Bae, S.C. Jeon*, K.H. Kim*, G.S. Lee*, J.S. Oh*, Y.C. Park*, W.H. Bae*, J.J. Yoo*, J.M. Yang*, H.M. Lee* and Y.-K. Choi
Korea Advanced Institute of Science and Technology and *Korean National Nanofab Center, Korea

17:05

8B-5
Quantum Confinement Effect for Efficient Hole Injection in MONOS-Type Nonvolatile Memory - the Role of Ultrathin i-Si/P+ Poly-Si Stacked Gate Structure Fabricated by Laser Spike Annealing
abstract I. Yanagi, T. Mine, A. Shima, S. Saito, D. Hisamoto and Y. Shimamoto
Hitachi Ltd., Japan
back to conference schedule
Wednesday, June 13
20:00

Rump Sessions: [Suzaku]
Organizers Meishoku Masahara, AIST
Robert Chau, Intel Corporation

J-R

Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

Organizers

  S. Odanaka, Osaka University
  R. Rios, Intel
  S. Kumashiro, NEC Electronics
  A. Bhavnagarwala, IBM

Moderators

  M. Hane, NEC
  K. Zhang, Intel

Panelists

  H. Masuda, Renesas
  M. Patyra, Intel
  C. Radens, IBM
  A. Amerasekera, Texas Instruments
  J. Farrell, AMD
  H. Yoshimura, Toshiba
 Compact models play a key role in DFM era, especially in variability-aware LSI design. There are questions as to the capabilities of these models, effectiveness in design, and credibility when design is concurrent with process development. The panel addresses some key questions.

- Are empirical Spice models sufficient or do we need to invest on better physical models for new materials and device architecture?
- Can we trust these models calibrated with limited process data?
- How do we accurately account for variations when design is concurrent to process development?
- How do we properly distinguish between systematic and random variations?
- Can we trust physical OPC, etching, and CMP models for predictions?
- Do the Spice variation models even matter when there are so many other sources of errors such as tool limitations, crude static timing assumptions, MCF approximations, and the exclusion of MIS and crosstalk?

R-1

Navigating the Roadmap to 32nm and Beyond: Breaking the Barriers [Shunju I, II]

Moderators
  S. Inaba, Toshiba
  R. Arghavani, AMAT

Panelists

  G. Shahidi, IBM
  M. Liang, TSMC
  Y. Toyoshima, Toshiba
  Y. Nishi, Stanford Univ.
  R. Chau, Intel
  T. Skotnicki, STMicroelectronics
  The transition to sub-90 nm node shifted a paradigm in logic LSI. Traditional device scaling methods failed to boost sufficient performance to uphold Moore’s Law. The 90 nm node, therefore, debuted with uniaxial strain engineering to improve device performance. The final scaled gate oxynitride dielectric (<5 atomic layers thick) was also introduced.
  The 65 nm node continued this scaling path with more enhanced stress inducing films in the front end. Gate dielectric was only slightly scaled at this node.
  Initial 45 nm node announcements indicate the introduction of immersion lithography, multiple strain inducing films, which use the additivity aspect of various strain inducing films, and PVD hard masks which enhance CD control. The introduction of high-κ gate dielectric and metal gate at 45 nm node is hailed as the “biggest
change to computer chips in 40 years”.
  Extrapolation of existing device trends shows significant barriers to the 32 nm technology node. Uniaxial process-induced strain engineering methods, based on new families of ultra-high stress inducing films combined with embedded SiGe or embedded Si:C structure at the source/drain, hold promise for achieving 32 nm node device targets. Other process area advances may assist in hitting this mark such as: low resistivity contacts, dual silicides, low-κ spacers, single wafer cleans to reduce defect density and eCMP methods with
chemistries to reduce variability in lithography and etch.
  This panel discussion addresses various technologies and lead 32 nm enabling options for further improving CMOS performance. Which sub 32 nm transistor structures are most viable for logic and SRAM applications? What does the future hold for High-κ and Metal gate? What are the emerging challenges in device parasitics?
What material selection guidelines will keep compatibility between generations? How to control the device characteristic variability?
  The distinguished panelists will also debate the viability of the above techniques to extend Moore’s Law toward 32 nm node and beyond.

R-2

The Status and Prognosis for High-κ/ Metal Gate Transistors [Shunju III]

Moderators

  Y. Nara, Selete
  J.C. Lee, The University of Texas at Austin

Panelists
  M. Bohr, Intel
  U-I. Chung, Samsung
  K. Imai, NEC Electronics
  M. Khare, IBM
  B.-H. Lee, SEMATECH
  Y. Tsunashima, Toshiba
  Silicon dioxide has been used as gate dielectrics and now scaled to ~1.2nm thick in typical 65nm process. As gate dielectrics are scaled, leakage currents increase (note: 1.2nm SiO2 consists of only 5 atomic layers). Thus, high-κ (high permittivity) dielectrics have been proposed as alternatives for gate dielectrics application in order to address the leakage problem, while maintaining high capacitance. The most common high-κ material studied so far is hafnium-based dielectric (e.g. HfO2, HfSixOy). However, high-κ gate dielectrics are not compatible with polysilicon gate electrodes commonly used in today’s integrated circuit technology. The combination leads to Fermi level pinning and phonon scattering problems. Thus, metal gate electrodes with appropriate work functions (one for NMOSFET and one for PMOSFET) would have to be used. Metal gate electrodes also improve the transistor characteristics by avoiding the so-called poly-depletion effects. However, implementing high-κ dielectrics and metal gate into CMOS technology is by no means an easy task. One has to address many technical issues such as deposition methods, dielectrics reliability, charge trapping and interface quality. Recently, semiconductor companies have announced a successful implementation of high-κ metal gate into their 45nm technology. Our panelists will present and discuss their view on the “status and prognosis for high-κ / metal gate transistors”. We will address the following questions:
-When will high-κ / metal gate products be first introduced in the market and for what applications?
-When will high-κ / metal gate products be more than 50% of the market?
-What are the remaining issues for high-κ/ metal gate process?
-What is the most suitable process for high-κ / metal gate (e.g. deposition methods, materials, gate-first or gate-last)?
-What is the cost of implementation of high-κ / metal gate processes?
-What is the biggest leverage of high-κ / metal gate process, performance increase, power reduction or scaling?
back to conference schedule
Thursday, June 14

Session 9A

Metal / FUSI Devices [Shunju I]
Chairpersons Y. Takao, Fujitsu Ltd.
D. Nayak, Xilinx Inc.

8:30

9A-1
Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
abstract H.R. Harris*, P. Kalra****, P. Majhi*, M. Hussain, D. Kelly, J. Oh, D. He, C. Smith, J. Barnett, P.D. Kirsch***, G. Gebara*****, J. Jur******, D. Lichtenwalner******, A. Lubow*******, T.P. Ma*******, G. Sung********, S. Thompson********, B.H. Lee***, H.-H. Tseng and R. Jammy***
SEMATECH, *AMD, **Intel, ***IBM, ****Univ. of California-Berkeley, *****ATDF, ******NC State Univ., *******Yale Univ. and ********Univ. of Florida, USA

8:55

9A-2
A Novel Hafnium Carbide (HfCx) Metal Gate Electrode for NMOS Device Application
abstract W.S. Hwang, C. Shen, X.P. Wang, D.S.H. Chan and B.J. Cho
National University of Singapore, Singapore

9:20

9A-3
Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS
abstract A. Shickova*, T. Kauerauf*, A. Rothschild, M. Aoulaiche*, S. Sahhaf*, B. Kaczer, A. Veloso, C. Torregiani*, L. Pantisano, A. Lauwers, M. Zahid*,*******, T. Rost**, H. Tigelaar***, M. Pas***, J. Fretwell****, J. McCormack****, T. Hoffmann, C. Kerner, T. Chiarella, S. Brus, Y. Harada*****, M. Niwa*****, V. Kaushik******, H. Maes*, P.P. Absil, G. Groeseneken*, S. Biesemans and J.A. Kittl**
IMEC, *KU Leuven, Belgium, **Texas Instruments assignee to IMEC, ***Texas Instruments, ****KLATencor, USA, *****Matsushita, ******Freescale assignees to IMEC, Japan and *******JMU, UK

9:45

9A-4
Gate First Metal-Aluminum-Nitride PMOS Electrodes for 32nm Low Standby Power Applications
abstract H.-C. Wen, S.C. Song, C.S. Park, C. Burham*****, G. Bersuker, K. Choi, M.A. Quevedo-Lopez*, B.S. Ju, H.N. Alshareef*, H. Niimi*, H.B. Park**, P.S. Lysaght, P. Majhi***, B.H. Lee**** and R. Jammy****
SEMATECH, *Texas Instruments, **SAMSUNG, ***Intel , ****IBM Assignees at SEMATECH and *****The University of Texas at Austin, USA
back to conference schedule
(Break 10:10-10:30)
Thursday, June 14

Session 9B

Novel DRAM Technology I [Shunju II]
Chairpersons J. T. Moon, Samsung Electronics Co., Ltd.
K. Parekh, Micron

8:30

9B-1
Improved Cell Performance for Sub-50 nm DRAM with Manufacturable Bulk FinFET Structure
abstract D.-H. Lee, S.-G. Lee, J.R. Yoo, G.-H. Buh, G.H. Yon, D.-W. Shin, D.K. Lee, H.-S. Byun, I.S. Jung, T.-S. Park, Y.G. Shin, S. Choi, U.-I. Chung, J.-T. Moon and B.-I. Ryu
Samsung Electronics Co. Ltd., Korea

8:55

9B-2
A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a Pad-Polysilicon Side Contacts (PSC)
abstract S.Y. Han, J.M. Park, S.O. Sohn, J.B. Lee, K.S. Chae, C.H. Jeon, J.S. Park, S.D. Kim, W.J. Kim, S. Yamada, Y.P. Kim, H.S. Park, N.M. Cho, H.H. Kim, M.S. Lee, Y.S. Lee, W. Yang, D. Park and B.-I. Ryu
Samsung Electronics Co., Korea

9:20

9B-3
Floating Body DRAM Characteristics of Silicon-On-ONO (SOONO) Devices for System-on-Chip (SoC) Applications
abstract C.W. Oh, N.Y. Kim, H.J. Song, S.I. Hong, S.H. Kim, Y.L. Choi, H.J. Bae, D.U. Choi, Y.S. Lee, D.-W. Kim, D. Park and B.-I. Ryu
Samsung Electronics Co., Korea

9:45

9B-4
Low Voltage/Sub-ns Operation Bulk Thyristor-SRAM (BT-RAM) Cell with Double Selective Epitaxy Emitters (DEE)
abstract T. Sugizaki, M. Nakamura, M. Yanagita, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, S. Kanda, K. Yagami and T. Oda
Sony Corporation, Japan
back to conference schedule
(Break 10:10-10:30)
Thursday, June 14
Session 10A
CMOS Platform / Integration Technology [Shunju I]
Chairpersons Y. Mochizuki, NEC Corp.
B. van Schravendijk, Novellus Systems, Inc.

10:30

10A-1
Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform
abstract K. Sukegawa, T. Yamamoto, H. Kudo, T. Kubo*, T. Sukegawa*, H. Ehara*, H. Ochmizu, M. Fukuda, Y. Mizushima, Y. Shimoda*, M. Tajima*, M. Oryoji*, Y. Nakata, H. Watatani, H. Sakai*, A. Asneil*, S. Sakai, H. Matsuyama*, H. Kurata, A. Tsukune, N. Shimizu, T. Futatsugi, S. Satoh, M. Kase* and T. Sugii
Fujitsu Laboratories Ltd. and *Fujitsu Limited, Japan

10:55

10A-2
A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node
abstract G. Tsutsui, S. Maruyama, T. Abe, H. Nakamura and T. Fukase
NEC Electronics Corporation, Japan

11:20

10A-3
Manufacturability and Speed Performance Demonstration of Porous ULK (k=2.5) for a 45nm CMOS Platform
abstract E. Richard, R. Fox*, C. Monget