Press Kit
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The following press materials are available for pre-conference publicity for the 2017 Symposia on VLSI Technology & Circuits
Press Releases
VLSI Symposia 2017 Lead Release and Technical Tip Sheets - April 27, 2017
English
- VLSI Symposia 2017 Lead Release (English) - April 27, 2017
- VLSI Symposia 2017 Technical Tip Sheet (English) - April 27, 2017
Japanese
- VLSI Symposia 2017 Lead Release (Japanese) - April 27, 2017
- VLSI Symposia 2017 Technical Tip Sheet (Japanese) - April 27, 2017
Chinese
- VLSI Symposia 2017 Lead Release (Chinese) - April 27, 2017
- VLSI Symposia 2017 Technical Tip Sheet (Chinese) - April 27, 2017
Korean
Images
- VLSI Technology Symposium 2017 logo (.jpg)
- VLSI Circuit Symposium 2017 logo (.jpg)
- Paper T2-3, A Low-Power Cu Atom Switch Programmable Logic Fabricated in a 40nm-node CMOS Technology (.jpg)
- Paper T5-1, Wafer Level Integration of an Advanced Logic-Memory System Through 2nd Generation CoWoS Technology (.bmp)
- Paper T6-1, Highly Manufacturable 7nm FinFET Technology featuring EUV lithography for Low Power and High Performance Application (.jpg)
- Paper T6-2, 10nm High Performance Mobile SoC Design and Technology Co-Developed for Performance, Power, and Area Scaling (.jpg)
- Paper T6-3, First Demonstration of Flash RRAM on Pure CMOS Logic 14nm FinFET Platform Featuring Excellent Immunity to Sneak-path and MLC Capability (.jpg)
- Paper T6-4, First Demonstration of 3D SRAM Through 3D Monolithic Integration of InGaAs n-FinFETs on FDSOI Si CMOS with Inter-layer Contacts (.jpg)
- Paper T8-1, Towards a Fully Integrated, Wirelessly Powered, and Ordinarily Equipped On-lens System for Successive Dry Eye Syndrome Diagnosis (.jpg)
- Paper T9-1, High Performance and Record Subthreshold Swing Demonstration in Scaled RMG SiGe FinFETs with High-Ge-Content Channels Formed by 3D Condensation and a Novel Gate Stack Process (.jpg)
- Paper T12-1, Nano-scaled Ge FinFETs with Low Temperature Ferroelectric HfZrOx on Specific Interfacial Layers Exhibiting 65% S.S. Reduction and Improved ION (.jpg)
- Paper JFS3-3, Performance Boost of Crystalline In-Ga-Zn-O Material and Transistor with Extremely Low Leakage for IoT Normally-Off CPU Application (.jpg)
- Paper T13-1, Towards Quantum Computing in Si MOS Technology: Single-shot Readout of Spin states in a FDSOI Split-Gate Device with Built-in Charge Detector (.jpg)
- Paper C2-1, BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator in 65 nm CMOS (.jpg)
- Paper C4-1, A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control (.jpg)
- Paper C8-1, A 16nm 69dB SNDR 300MSps ADC with Capacitive Reference Stabilization (.jpg)
- Paper C9-1, A 1.06 uW Smart ECG Processor in 65 nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring (.jpg)
- Paper C11-1, A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier (.jpg)
- Paper JFS2-1, A Digitally Controlled Fully Integrated Voltage Regulator with 3D-TSV Based On-Die Solenoid Inductor with Backside Planar Magnetic Core in 14nm Tri-Gate CMOS (.jpg)
- Paper C12-2, A 0.3V VDDmin 4+2T SRAM for Searching and In-Memory Computing Using 55nm DDC Technology (.jpg)
- Paper C14-1, A 0.5V 1.6mW 2.4GHz Fractional-N All-Digital PLL for Bluetooth LE with PVT-Insensitive TDC using Switched-Capacitor Doubler in 28nm CMOS (.jpg)
- Paper C19-1, A 4.1Mpix 280fps Stacked CMOS Image Sensor with Array-Parallel ADC Architecture for Region Control (.pdf)
- Paper C20-1, Recryptor: A Reconfigurable In-Memory Cryptographic Cortex-M0 Processor for IoT (.jpg)
- Paper C23-1, A 100mW 3.0 Gb/s Spectrum Efficient 60 GHz Bi-Phase OOK CMOS Transceiver (.jpg)
- Paper C24-1, A 10.1" 56-Channel, 183 uW/electrode, 0.73 mm2/sensor High SNR 3D Hover Sensor Based on Enhanced Signal Refining and Fine Error Calibrating Techniques (.jpg)
- Paper C25-1, A 32Gb/s, 4.7pJ/bit Optical Link with -11.7dBm Sensitivity in 14nm FinFET CMOS (.jpg)
- Paper C25-2, A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET (.jpg)
- Paper C26-2, A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks (.jpg)
Press Registration
Registration at the 2017 Symposia on VLSI Technology & Circuits is complimentary for the press. If you plan to attend, please download the press registration form, and fax or mail the completed one to the VLSI Secretariat (Japan and Asia) at vlsisymp[at]ics-inc.co.jp. Please prepare to show a business card when you arrive at the Symposia.
If you have any registration/attendance questions, please contact the Secretariat.
Editor Contact
Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact the Publicity chairs or the Secretariat for additional information or interviews you may need.
Ken Uchida
JFE Technology Publicity Chair
uchidak[at]elec.keio.ac.jp
Kazuhisa Sunaga
JFE Circuits Publicity Chair
k-sunaga[at]ak.jp.nec.com