Forum
Compute Paradigms for Secured Microelectronics and Combinatorial Optimization [Suzaku I+II+III]
Chairpersons: S. Yu, Georgia Institute of Technology
Chairpersons: M. Takamiya, The Univ. of Tokyo
Chairpersons: S. Fujii, Kioxia Corp.
Date & Time: Friday, June 16, 8:50A.M.-3:00P.M.
- 8:50 Opening by Forum Chair
- 8:55 Cyber-Physical Security from Chip to Cloud, T. Perianin and V. Yli-Mäyry, Secure-IC
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Abstract:
To ensure a fully managed and secure end-to-end cybersecurity solution, it is necessary to have full control over the product lifecycle and its security.
Lifecycle management solutions cover the different stages of a product life: from IC design, security evaluation and certification, manufacturing to field deployment and then the decommissioning of devices that include those ICs. To ensure the security at all stages, Secure-IC offers a fully comprehensive solution that ensures product security is maintained, and that each stakeholder only has access to the relevant functions and services at each step of the product’s life.
Especially for connected devices lifecycle management, a complete chip to cloud solution that enables provisioning, device management, device monitoring and device identity management, and offers differentiated security services for chip manufacturers and users can bring high additional value to the products. This approach comes in combination with having a scalable integrated Secure Element on the Embedded Edge device side.
The challenge of lifecycle security management is also now impacted by the emergence of PQC (Post-Quantum Cryptography).
Secure-IC will address those questions and propose an approach from chip security hardware solution to Chip-to-Cloud complete security solution.
- 9:25 In-Memory-Computing Based Accelerators for Secure Computing, X. S. Hu, CISE CCF, National Science Foundation
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Abstract:
High-throughput and low-energy secure information processing are in high demand due to the increasing needs for privacy in edge computing applications. As many encryption/decryption/privacy-preserving computing (PPC) algorithms involve operations on a massive amount of data, in-memory computing (IMC), where certain computations are performed in memory, can be an effective architectural approach for accelerating such algorithms. IMC accelerators can further benefit from emerging memory technologies. This talk presents two IMC accelerators for PPC: IMCRYPTO, a programmable fabric for accelerating block ciphers for data encryption/decryption, and PPIMCE, an extension to IMCRYPTO, for accelerating both homomorphic encryption (HE) and Garbled Circuits (GC), two important PPC techniques that support direct computations on encrypted data. These fabrics build on an IMC design called random-access/content-addressable memory, which can be accessed with either addresses or data. The throughput and energy benefits of these IMC fabrics are demonstrated by applying the fabrics to accelerate a typical neural network workload.
- 9:55 Cryptographic Circuit Technology Consisting of Photonic Logic Gates, J. Takahashi, NTT Social Informatics Laboratories
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Abstract:
Photonic computing has attracted much attention because it can achieve low latency and provide low-power processing capabilities in All-Photonic Network (APN) platforms. To ensure the security of such platforms, security functions such as cryptography and authentication are required. We investigate cryptographic circuits consisting of photonic logic gates for use in data encryption and authentication in photonic computing and photonic information communications on the APN. In this talk, we will discuss methods of implementing cryptographic circuits using photonic logic gates for standard block ciphers and introduce fabricating photonic circuit with a nonlinear function of the cipher such as a substitution box. We consider that the photonic cryptographic circuits with low latency and low-power consumption are feasible in the future. Furthermore, these studies will contribute the development of digital calculation methods based on photonic processing.
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10:25
Looking Beyond Cryptography: Side-Channel Attacks (and more) on Machine Learning Accelerators,
S. Bhasin, Nanyang Technological University -
Abstract:
The huge demand for machine (and deep) learning applications has motivated deployment of dedicated accelerators to support the high workload. These accelerators can be in form of special microcontrollers, FPGA, ASICs as well as GPUs. However, running machine learning on such dedicated hardware leads to new threat vectors. In this talk, we explore the landscape of practical side-channel attacks on machine learning accelerators. We show how side-channel attacks can be used to reverse engineer architectures and parameters of deep learning models from hardware of all complexities. For instance, we show its possible to recover architecture of the machine learning model in a single side-channel trace, even on complex hardware like FPGA and GPU. Further, we demonstrate practical and low-cost cold boot based model recovery attacks on Intel Neural Compute Sticks 2 (NCS2) to recover the model architecture and weights, loaded from the Raspberry Pi with high accuracy. Finally, we discuss some mitigation techniques. - 10:55 Panel Discussion for Secured Microelectronics
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Abstract:
In semiconductor manufacturing, a wide variety of tuning knobs control the processes. Optimization of these processes becomes a serious problem due to the associated complexity of their nature as well as the correlation between each tuning parameter. machine learning has recently drawn the attention of engineers due to its promising characteristics as a powerful tool for the optimization of these parameters. machine learning technique applied in this study is based on a regression algorithm for optimization, particularly of the deposition process condition and the plasma distribution control knob, the latter being related to the uniformity of film thickness and etch rate within a wafer, which are important properties in semiconductor manufacturing. The machine learning approach is useful because it allows the exploration of a new process window. - 11:40 Lunch
- 12:40 Quantum-Inspired Annealing Processor, C. H. Kim, Univ. of Minnesota
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Abstract:
In this talk, I will first provide an overview of Ising machines, quantum annealers, coupled oscillators, and combinatorial optimization problems. Then, I will introduce my team's recent advances in developing quantum-inspired CMOS Ising chips that can solve hard optimization problems aimed by both quantum annealers and probabilistic algorithms. Finally, I will discuss the current challenges we face in designing these unique chips and highlight the future research directions we plan to explore. -
13:10
Simulated Bifurcation Machines: Combinatorial Optimization Accelerators Based on a Quantum-Inspired Parallelizable Algorithm,
K. Tatsumura, Toshiba Corp. -
Abstract:
Practically important problems such as decision-making and planning can often be formulated into combinatorial optimization. Many combinatorial optimization problems are classified as non-deterministic polynomial-time hardness. Simulated bifurcation (SB) is a quantum-inspired heuristic algorithm for combinatorial optimization, which was found as a classical counterpart of bifurcation-based adiabatic quantum computation with a nonlinear oscillator network. The SB algorithm is highly parallelizable and thus can be accelerated with massively parallel processors such as FPGAs (field-programmable gate arrays). This talk will give a comprehensive review of the SB, including the basis of SB algorithm (where it came from, how it works, and the algorithmic parallelism), efficient and scalable FPGA-based implementations (single- and multi-chip), and the applications toward innovative real-time systems that make optimal responses to ever-changing situations. An example of those applications is a financial high-speed trading machine that detects profitable trading opportunities based on combinatorial optimization and issues order packets at microsecond speeds. - 13:40 Flexible Optimization Solver Using Mixed Analog-Digital In-Memory Computing, J. P. Strachan, RWTH Aachen
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Abstract:
There is active research by multiple communities building hardware accelerators for combinatorial optimization. The emerging approaches combine different computing models (Ising models, continuous time nonlinear equations, quantum adiabatic evolution, etc) with physical hardware primitives (optical oscillators, magnetic tunnel junctions, CMOS circuits, superconducting qubits, etc). Despite a diversity of approaches, the underlying requirements to address the extreme challenges in optimization problems remain similar. These include support for high connectivity, sufficient precision, scalability to large problems, and flexible support for emerging algorithmic improvements. I will describe our proposed hardware and algorithmic approach that is based on mixed analog-digital memristor-based circuits implementing Hopfield neural network dynamics. We augment Hopfield networks to support higher order interactions, as needed for many problem classes, as well as constraint enforcement. The platform supports multiple forms of annealing, including stochastic, quantum-inspired, chaotic, and weight annealing. I will describe performance and some of the issues encountered in solving 3SAT problems with such a hardware platform and comparisons to the state-of-the-art. - 14:10 Engineering for Large-Scale Superconducting Quantum Annealers, S. Kawabata, AIST
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Abstract:
Quantum annealing is a promising technique which leverages quantum mechanics to solve hard combinatorial optimization problems. D-Wave Systems Inc. is the first company to commercialize superconducting quantum annealing machine in 2011 and will ship a new machine with 7000 qubits in 2023. However, integration of larger number of qubits as well as improvement of qubit coherence are required for practical applications. In this talk we will overview our technological integration scheme for large-scale superconducting quantum annealing machine in AIST. In addition, we will show a fabricated superconducting quantum annealer AQUA1.1 (superconducting integrated circuit using Nb flux qubit) for prime factoring, experimental results of quantum annealers at 10mK, and numerical thermal simulation of 2.5D integrated quantum circuits. - 14:40 Panel Discussion for Combinatorial Optimization
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Abstract:
Semiconductor technologies have advanced chiefly because of our exponentially increasing needs for computation, data storage and data communication. These powerful technologies can be leveraged in a myriad of ways to enable novel healthcare applications. I will discuss repurposing of devices at the nanoscale for high-throughput omics applications, a chip-based programmable organ-on-chip approach, and a novel SARS-CoV-2 diagnostics approach that detects the virus in exhaled particles using a simple breath test. The relevance of these systems in a post-COVID world will be highlighted. - 15:25 Closing by Forum Chair
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Abstract:
Semiconductor technologies have advanced chiefly because of our exponentially increasing needs for computation, data storage and data communication. These powerful technologies can be leveraged in a myriad of ways to enable novel healthcare applications. I will discuss repurposing of devices at the nanoscale for high-throughput omics applications, a chip-based programmable organ-on-chip approach, and a novel SARS-CoV-2 diagnostics approach that detects the virus in exhaled particles using a simple breath test. The relevance of these systems in a post-COVID world will be highlighted.