Short Course 1 | Symposium on VLSI Technology and Circuits

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Advanced CMOS Technologies for 1 nm & Beyond

Chairpersons: K. Tomida, Rapidus Corp.
Chairpersons: Y. Liang, NVIDIA Corp.

Date & Time: Monday, June 12,　8:25A.M.-5:00P.M.

8:25 Introduction
8:30 Advanced CMOS Transistor Scaling towards 1nm Node and Beyond, Chung-Hsun Lin, Intel Corp.: Abstract:
As FinFET scaling comes to an end in 3nm node, there are several innovative device and standard cell architectures considered for 2nm node and beyond: from gate-all-around (GAA) transistor, backside power delivery, complementary FET (CFET), to atomic channel FET with 2D materials. The GAA transistor is the most pragmatic architecture in the near term to enable incremental contact-poly pitch and gate length scaling because of its limited perturbation to a conventional FinFET process integration and design flows. Backside power delivery and CFET (3D stacking) technology brings additional cell level area scaling benefit as well as heterogeneous integration benefit for high mobility channel enablement. 2D material FET provides the ultimate gate length scaling with high mobility channel capability. In this short course, we will focus on technology and device design value proposition for these innovations with the corresponding engineering opportunities and challenges for high volume manufacturing.

About Chung-Hsun Lin

Chung-Hsun Lin is Senior Director and Technology Performance Manager on leading edge technologies in Logic Technology Development at Intel. His current role is in the overseeing the development and performance of Intel’s RibbonFET and PowerVia. His team is responsible for technology definition, transistor performance, test chip integration, PDK model targets, and customer engagement. Before he joined Intel, Chung-Hsun led several advanced technology development and exploratory device research projects at GlobalFoundries and IBM, including the delivery of 22nm Planar SOI and 14nm FinFET on SOI technologies for high performance computing. Chung-Hsun received his Ph.D. degree in electrical engineering and computer sciences from the University of California, Berkeley and his B.S/M.S degrees in electrical engineering from National Taiwan University, Taiwan. His Ph.D. work contributed to the first industrial standard FinFET compact model: BSIM-CMG. Chung-Hsun holds over 135 US patents and has published over 70 papers in accredited journals and international conferences in semiconductor technology.
9:20 Advances in EUV Lithography: From 0.33NA Technology towards High-NA and Beyond, E. van Setten, ASML: Abstract:
DUV lithography has been the workhorse for the industry for the past decades. Multiple customers have now entered the high volume manufacturing phase with EUV lithography using ASMLs NXE scanners. To enable further cost-effective scaling, ASML and Zeiss developed the next generation High-NA EUV platform with an NA of 0.55, that builds on the EUV technology developed on the 0.33NA platform.
In this short course we will give an overview of the current status of 0.33NA EUV technology and the next generation High-NA EUV platform, including a historic perspective. We illustrate how the learnings from the past are being applied and what new technologies are being developed to drive the EUV lithography roadmap. We will cover advances in scanner development, such as source and optics, but also developments in the eco-system, like mask, photoresist and OPC. We conclude with an outlook of what may come after High-NA EUV.

About Eelco van Setten

Eelco van Setten is a Principal Architect at ASML in Veldhoven. He received his MSc in Applied Physics from the University of Twente in the Netherlands in 1999 and joined ASML in 2000. He has worked on the evaluation and understanding of the imaging performance of ASML’s scanners for many generations and technology nodes, covering KrF, ArF, immersion and EUV. Currently he is working as System Engineer for EUV imaging on the development of ASML’s high NA EUV lithography tool with a special interest in EUV resolution enhancement techniques and the impact of the EUV mask stack on imaging performance. He is the author or co-author of 70+ conference papers and presentations.
10:10 Break
10:40 Advanced Logic Transistor Process Technology towards 1-nm Node, N. Yoshida, Applied Materials, Inc.: Abstract:
After several generations of FinFET scaling to the latest 3-nm node [1], advanced logic transistor architecture continues to evolve to horizontal gate-all-around (GAA) FET with vertically stacked Si nano-sheet (NS) channel [2, 3]. Multiple innovations of process technology are required for NS-GAA implementation in high volume manufacturing. Beyond NS-GAA and other scaling boosters such as backside power delivery, novel transistor architectures are in the pipeline for future CMOS scaling. One of the proposed new architectures is to vertically stack PMOS and NMOS, also known as CFET, for effective CMOS area scaling. CFET fabrication is proposed in mainly two different integration approaches, sequential and monolithic integration [4 - 6].
This short course describes process challenges and process technology solutions for GAAFETs as the next transistor inflection. In addition, we’ll discuss CFET process integration approaches and key technology innovations.

About Naomi Yoshida

Naomi Yoshida currently works on process integration in Semiconductor Products Group at Applied Materials. She worked in various technical fields over twenty-five years; covering metallization process engineering, electrical characterization, and process integration. In FEOL integration, she made key contributions to developing advanced high-k metal gate process solutions. In recent years, she has worked on developing process integration solutions for gate-all-around transistors, 3D-logic, and backside power-rail for beyond 3-nm advanced logic scaling. She received her master’s degree in physics from International Christian University in Japan. She has published more than forty peer-reviewed papers and has more than thirty granted patents.

11:30 Challenges and Innovations for Advanced BEOL Scaling at the 1nm Node and Beyond, C. Penny, IBM Corp.: Abstract:
For over twenty years, dual damascene copper interconnects have been the industry standard for advanced logic technologies. In this time, a continuous series of innovations has enabled scaling of the interconnect by a factor of 10. In recent years, however, the rate of scaling has slowed, and new advances will be needed to continue extending Moore’s Law. In this talk, I will discuss recent advances in interconnect research and the challenges that remain to continue scaling. Several recent innovations which enable the extension of the copper damascene integration scheme will be reviewed. I will also look at the options for scaling beyond copper damascene. Subtractive ruthenium has emerged as one of the most likely technologies to scale beyond copper. I will review the potential advantages of alternate metals, including ruthenium, as well as the challenges and advances that will enable scaling to the 1nm node and beyond.

About Chris Penny

Chris Penny is currently a Senior Engineer at IBM Research in Albany, leading the research for advanced interconnect scaling. After graduating from MIT in 2001 with a degree in Chemical Engineering, he joined IBM to support the startup of the 300mm manufacturing and development fab in East Fishkill, NY. Mr. Penny has supported development of the BEOL for every technology node for IBM since 65nm. He led the development of airgap technology, culminating in the demonstration of airgaps in 48nm pitch Cu interconnects. Most recently, he has led the development of advanced interconnects, with a focus on developing multipatterning-EUV solutions for 18nm pitch subtractive ruthenium interconnects with TopVia.
12:20 Lunch
13:10 CMOS Scaling by Backside Power Delivery, N. Horiguchi, imec: Abstract:
Current CMOS chips have both signal routing and power delivery in frontside of wafer. However, frontside power delivery has to go through multiple metal layers and wide power metal lines consume area, which cause IR drop and routing congestions, respectively. It is an attractive option to separate signal routing in frontside and power delivery in backside. It improves routing congestions and IR drop. Several backside power delivery options are proposed, and they have trade-offs in terms of process complexity, area scaling and IR drop. Backside power delivery integration requires extreme wafer thinning and metal connection from backside, which could cause challenges in integration control, such as wafer distortion and litho alignment, and device performance, such as channel stress and self-heating. Backside power delivery concept could be extended to functional backside, such as backside global interconnect and backside device, which enables further CMOS scaling by using backside engineering.

About Naoto Horiguchi

Naoto Horiguchi is the director of logic CMOS device program in imec, Leuven, Belgium. He started his carrier in semiconductor device R&D in Fujitsu Laboratories Ltd. in 1992. In 1992-1999, he was engaged in device R&D by using semiconductor nano structures in Fujitsu laboratories Ltd. and University of California, Santa Barbara. In 2000-2006, he was engaged in 90-45nm CMOS technology development in Fujitsu Ltd. From 2006, he is with imec, Leuven, Belgium, where he is engaged in advanced CMOS device R&D together with worldwide industrial partners, universities, and research institutes. His current focus is CMOS device scaling for 10Å technology node and beyond.
14:00 Process Control Solutions for the Era of 3D Architecture Devices, S. H. Han, Nova: Abstract:
As semiconductor devices continue to scale, the performance limitations of 2D architectures are driving the migration to 3D architectures. But in doing so, new challenges arise for process control solutions to detect potential variations in structure and in materials to maintain high quality processes for targeting performances.
This course will describe the latest metrology technologies and challenges in serving 3D device processes, teach participants how the shift from 2D to 3D architecture devices are resulting in new performance requirements for process control solutions, and cover principles of metrology concepts including the optical, X-ray, E-beam and scanning probe microscopy. This course will also teach the lab solution for in-line solutions for 3D process control analysis and cover new trends in problem solving in the metrology industry to address challenges for 3D devices, including machine learning techniques and hybrid metrology systems at high volume manufacturing.

About Sang Hyun Han

Sang Hyun is Nova Ltd.’s VP of strategic marketing defining product strategy, strategy for customer engagement, and leading regional marketing team.
Before joining Nova Ltd., Sang Hyun had previously held several positions, serving as product marketing & technical director at KLA from 2008 to 2019.
Prior to KLA, Sang Hyun had also worked for several semiconductor chip makers as various positions on yield engineering, devices, process integration, thin film, and diffusion groups from 1993 to 2008.
Sang Hyun earned Ph.D. in the material science from Iowa State University in US (1992), and M.S. in the metallurgic engineering from Seoul National University in South Korea (1985), and B.S. in the metallurgical engineering from Hanyang University in South Korea (1983).
14:50 Break
15:10 Semiconductor Packaging Revolution in the Era of Chiplets, Y. Orii, Rapidus Corp.: Abstract:
Since the semiconductor cost for state-of-the-art nodes is increasing, "Chiplet" technology is in the spotlight as a new evolutionary path to scale up integration and improve performance and reduce the total cost. With an SoC, a chip might incorporate a CPU, plus an additional several IP blocks on the same chip. That design is then scaled by the advanced node, which is an expensive process. With a chiplet model, those several IP blocks are hardened into smaller dies(chiplets) and those dies are integrated on an interposer to build a system. Those chips must be connected in the shortest length while considering signal integrity and power integrity so that the cutting-edge packaging technology is the key to improve the performance of IT equipments. In this short course, the advanced 2.1D, 2.3D, 2.5D and 3D packaging technologies will be introduced as well as the several interposer technologies.

About Yasumitsu Orii

Dr. Yasumitsu Orii joined IBM Japan in 1986 and was a leading expert on Flip Chip organic packages, which had contributed to the performance improvements and miniaturization of such products as servers, laptop computers, and HDDs. The packaging technology is becoming more important for next generation server products as Moore’s Law reaches its limits. His flip chip expertise extended into many related areas. Initially, he was a pioneer of flip chip on FPC (Flexible Printed Circuit) for HDDs, which allowed the read/write amplifier ICs to be mounted on the suspension and much closer to the GMR head. Later, he developed the C2 (Chip Connection) technology that supported low-cost 50-μm-pitch flip chip bonding for the commodity consumer electronics market and it was licensed to a company in Taiwan. At IBM Research Tokyo, he was leading the next generation flip chip organic package, 3D-IC projects and Neuromorphic Computing for IBM Servers and creating new technologies under a Joint Development Program involving many leading Japanese materials companies. He left IBM in 2014 and joined NAGASE & CO., LTD. He established “New Value Creation Office” under the direct control of the president and launched the material informatics software as a service in 2020. He left NAGASE and he joined Rapidus Corporation in 2022/Dec. Now he is the senior managing executive officer to lead the 3D Assembly Division.
16:00 Device Technology for 2D Layered Semiconductor FETs: Challenge & Perspective, K. Nagashio, The Univ. of Tokyo: Abstract:
Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. The circuits consisting of more than 50k transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. Moreover, the successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration has been demonstrated last year. While steady progress has been made on 2D integration technology, some bottlenecks are still present. In this short course, the present status and the perspective on the 2D electronics will be discussed.

About Kosuke Nagashio

Kosuke Nagashio received the B.E. degree in Materials Science & Engineering from Kyoto University in 1997 and the M.E. and Ph.D. degrees in Materials Engineering from The University of Tokyo in 1999 and 2002, respectively. From 2002 to 2003, he was a postdoctoral research fellow at Stanford University, California. He is currently a Professor with the Department of Materials Engineering, The University of Tokyo. His research interests presently focus on the carrier transport in 2D materials and the crystal growth of 2D materials. Dr. Nagashio is a member of the Japan Society of Applied Physics (JSAP), the Materials Research Society (MRS), the IEEE Electron Device Society (EDS) and the American Physics Society (APS).