Short Course 2 | Symposium on VLSI Technology and Circuits

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Future Directions in Highspeed Wireline/Optical IO [Suzaku I+II]

Organizers: K. Yoshioka, Keio Univ.
Organizers: C. Tokunaga, Intel Corp.

Date & Time: Monday, June 12,　8:25A.M.-5:00P.M.

Chairpersons: T. Iizuka, The University of Tokyo
Chairpersons: N. Kocaman, Broadcom Ltd, Inc.

8:25 Introduction

8:30 Industry Megatrends Driving Connectivity R&D, T. C. Carusone, Univ. of Tronto / Alphawave Semi: Abstract:
Progress in computation and communication is increasingly bottlenecked by integrated circuit I/O. Industry megatrends are increasing connectivity demands overall, and spawning new, increasingly critical applications for die-to-die and optical links. Die-to-die links demand the ultra low power and area, while our highest-speed interfaces now incorporate full-fledged digital modems operating over 100 Gbps. This presentation provides an overview of this diverse technology landscape and the emerging solutions in each sector, providing a foundation for the talks that follow.

About Tony Chan Carusone

Dr. Tony Chan Carusone has taught and researched integrated circuits and systems in academia and industry for over 20 years. He has been a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He and his graduate students have received eight conference best-paper awards for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. He has also been a consultant to industry since 1997, and in 2022 became the Chief Technology Officer of Alphawave Semi in Toronto, Canada.
Dr. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and served on the Technical Program Committee of the International Solid-State Circuits Conference from 2015-2021. He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters. He is a Fellow of the IEEE.

9:20 SerDes System Design, T. Toifl, Cisco Systems: Abstract:
This talk intends to give an overview of system design options for next generation high-speed SerDes designs. Starting from system modelling, we will describe the relevant options to reduce BER at high data rates, such as advanced DFE, duobinary signaling, MLSE and FEC coding, and show examples of current implementations. We will then describe several routes to possibly enhance data rates in the future, such as multi-wire differential transmission, simultaneous bi-directional and discrete multi-tone signaling.

About Thomas Toifl

Thomas Toifl (S’97–M’99–SM’09) received the Dipl.-Ing. (M.S.) degree and the Ph.D. degree (Hons.) in electrical engineering from the Vienna University of Technology, Vienna, Austria, in 1995 and 1999, respectively. In 1996, he joined the Microelectronics Group, European Research Center for Particle Physics (CERN), Geneva, Switzerland, where he developed radiation-hard circuits for detector synchronization and data transmission, which were integrated in the four particle detector systems of the Large Hadron Collider (LHC). In 2001, he joined the IBM Research–Zurich, Rüschlikon, Switzerland, where he has been involved in multi-gigabit per second, low-power communication circuits in advanced CMOS technologies since 2001. He has authored or co-authored numerous patents and 95 technical publications in these areas. He was the Manager of the I/O Link Technology Group, IBM Research–Zurich, from 2008 to July 2018. In 2018 he joined Cisco Systems, Thalwil, Switzerland, where he leads the local circuit design team. Dr. Toifl was a recipient of the Beatrice Winner Award for Editorial Excellence at the 2005 IEEE International Solid-State Circuits Conference (ISSCC). He previously served on the TPC of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), and the European Solid-State Circuits Conference (ESSCIRC), and since 2019 serves on the TPC of ISSCC.
10:10 Break
10:40 Trends in Digital Coherent Technologies with DSP ASICs for Optical Communication Systems, F. Hamaoka, NTT Network Innovation Laboratories: Abstract:
To cope with the rapid growth in communication traffic, the capacity of optical transmission systems has continued to increase, as helped along by breakthroughs such as wavelength-division multiplexing and digital coherent technologies fully utilizing the capability of light waves by powerful digital signal processing (DSP). Digital coherent technologies with DSP application-specific integrated circuits (ASICs) support multi-rate and multi-modulation formats to meet the demands of multiple applications including long-haul, metro, and short-reach networks. Recently, a cutting-edge DSP for supporting up to 1.2 Tbps/carrier for digital coherent systems has been announced. This short course provides an overview of the trends in digital coherent technologies with DSP ASICs. It also presents our recent research and development pertaining to high-speed and high-capacity transmission utilizing digital coherent technologies.

About Fukutaro Hamaoka

Fukutaro Hamaoka received his B.E., M.E., and Ph.D. in electrical engineering from Keio University, Kanagawa, in 2005, 2006, and 2009. From 2009 to 2014, he was with NTT Network Service Systems Laboratories, where he was engaged in the R&D of high-speed optical communication systems, including digital coherent optical transmission systems. He is currently a Senior Research Engineer at NTT Network Innovation Laboratories. He was a tutorial speaker at OFC 2020 on the topic of “Ultra-wideband Transmission and High-symbol Rate Signal Handling Technologies”. His research interests include high-capacity optical transport systems with ultra-wideband WDM and high-symbol rate techniques based on digital coherent technologies.

11:30 Silicon Photonics Transceiver for High-Density Optical Interconnection, T. Nakamura, AIO Core: Abstract:
Silicon photonics technology is that it provides compact and low-cost photonics integrated circuits using strong optical confinement by silicon core and Si CMOS technology. In recent years, the growth of CPU/GPU performance has reached a ceiling due to the limit of gate miniaturization, and one of the ways to further increase computing power, especially for AI, is to connect many CPUs/GPUs and perform parallel distributed processing. For achieving those, low latency connections using high-speed, large-capacity optical interconnection are required. In this presentation, we will introduce compact, low-power, large-capacity optical interconnection transceivers from various companies that have been realized using silicon photonics technology. In addition, we will introduce the application of the high-temperature, highly reliable optical I/O core, that we have developed, to FPGA accelerators, PCIe, 5G antennas, and future automotive applications.

About Takahiro Nakamura

Takahiro Nakamura received the B.E., M.E., and D.E. degrees in electrical engineering from Osaka University in 1986, 1988, and 2005, respectively. He joined NEC Corporation, Kawasaki, Japan in 1988, where he engaged in research and development on laser diodes.
He has been a chief manager for the Photonics and Electronics Technology Research Association (PETRA) from 2009 to 2022, where he engaged in research and development on silicon photonics integrated circuits and their applications. He is currently a general manager of optical I/O core device technology in AIO Core Co., Ltd. He is a member of the Institute of Electronics, Information and Communication Engineers of Japan.
12:20 Lunch
13:10 Beyond the Interconnect, Challenges on the Way to Enabling Heterogenous Chiplets in Package, A. Kashem, Advanced Micro Devices, Inc. (AMD): Abstract:
As we further race to bring together heterogenous compute and acceleration from the motherboard to the package, our industry will need to solve several new challenges. UCIe is a great step forward to address the interconnect aspect, but what else do we need? What standard form factors should we define? How do we enable debug/test beyond KGD? What kind of power delivery and thermal controls will we need? Can we also enable DVFS and binning? How do these challenges differ between advanced and organic packaging solutions? In this course, we will take a look at these questions and discuss some possible ways forward to address these challenges.

About Anwar Kashem

Anwar Kashem holds the position of CVP I/O Architecture at AMD, responsible for I/O subsystems and chiplet interconnect. He has extensive design experience designing the PHY and Logical layers for high speed parallel interfaces including GDDR, HBM, LPDDR, DDR, UCIe and internal chiplet interfaces. Anwar has received B.S. (2002) and M.Eng (2004) degrees from Cornell University. Prior to AMD, he was responsible for several families of DPUs and RAN accelerators at Marvell and Memory interface IP at Synopsys.
14:00 Architecture and Circuit Design of High-Speed Wireline Receivers, A. Balankutty, Intel Corp.: Abstract:
This short course will cover SerDes receiver design from first principles. We will review signal and noise budgeting for wireline systems, review ADC based receiver architectures for high-loss electrical links, design of analog front-end circuits and advanced equalization techniques for 100+Gb/s links.

About Ajay Balankutty

Ajay Balankutty received his B. Tech. degree from National Institute of Technology (India) and his M.S. and Ph.D. degrees in Electrical Engineering from Columbia University (USA). He is currently a Principal Engineer leading the Serial I/O development team at Advanced Design in Intel Corporation. His team develops SerDes architecture and circuits for next generation systems and standards, and performs design technology co-optimization (DTCO) of I/Os for each new Intel process. His current research interests include high-speed I/Os and RF/millimeter-wave circuits.
14:50 Break
15:10 Design Considerations for High-Speed Transmitters in Wireline and Optical Communications, A. Vasani, Broadcom Ltd.: Abstract:
With the Data Bandwidth need increasing exponentially with AI/ML application, there is significant pressure on the analog front end circuits to lower the power while achieving high bandwidth for both wireline as well as optical links. The port speeds are quickly moving towards 200G/lane and the TX is an important part of enabling the link quality and is also important in determining the efficiency and area improvements from one generation to another. This talk gives a general overview of various design blocks involved in the design of a TX; including Clocking, Muxing and Driver/DAC. It will also talk about the key performance metrics and how they fit into the link closure.

About Anand Vasani

Mr. Anand Vasani received the B.E. degree in industrial electronics from Pune University, India, in 2004 and the M.S.E.E. degree from the North Carolina State University, Raleigh, in 2006. Since 2006, he has been with Broadcom Inc’s Physical Layer Product Analog Group; where he is responsible for the design of analog CMOS blocks including TX, RX and PLLs. He has been leading the TX design effort for wireline as well as optical applications for rates up to 200G PAM4 application. Mr. Vasani has 7 issued patents. He has 13 publications in JSSC, ISSCC and VLSI.
16:00 Recent Developments and Challenges for NAND Flash Memory Interface, T. Toi, KIOXIA Corp.: Abstract:
The explosive increase in data used by machine learning applications and big data analysis is requiring high-bandwidth and large-capacity storage systems using NAND flash memories. Increased capacity of NAND flash memory has been driven by technologies for 3D architecture of memory cells and higher-level cells, while higher bandwidth of NAND flash memory interfaces, e.g., Toggle DDR and ONFi, has been realized by several techniques such as double data rate transfer, on-die termination and various calibrations. However, NAND flash memory interfaces have inherent challenges, and that makes it difficult to follow the high speed trends of host interfaces, e.g., PCIe and CXL, connecting a host CPU and a controller of a storage. Recently proposed topologies using additional bridge chips, which could replace conventional multi-drop bus topology of NAND flash memory interfaces, are expected to realize both high-bandwidth and large-capacity.
In this talk, the basic configuration and existing techniques of NAND flash memory interfaces will be introduced while discussing the differences against DRAM interfaces, leading in terms of transfer rate. Then, we will elaborate on latest published techniques to address challenges of NAND flash memory interfaces.

About Takashi Toi

Takashi Toi received the B.S. and M.S. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2014 and 2016, respectively. In 2016, he joined the Center for Semiconductor Research & Development, Toshiba Corporation, where he was involved in analytical understanding of jitter and phase noise of clock and data recovery circuits for high-speed wireline communication. In 2017, he moved to Institute of Memory Technology Research & Development, Kioxia Corporation, Kawasaki, Japan. His present research interests include ultra-high bandwidth Analog front-end circuits design for storage systems.