Workshop 2 | Symposium on VLSI Technology and Circuits

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EUV Lithography & Path to High NA EUV Patterning Solutions

Organizer: Allen Gabor (IBM)

EUV lithography has been used in high-volume production since 2019 and by 2025 high NA EUV is expected to be implemented. To achieve the theoretical resolution capability of EUV, and especially high NA EUV, both the high NA EUV tool and all the supporting infrastructure need to be developed. New resist materials and improved EUV masks are two key supporting infrastructure areas. The development of the high NA tool and its implications to chip design and layout are also critical for the semiconductor community to understand. This workshop will cover many aspects EUV and the transition to high NA EUV including.

About Allen Gabor

Allen Gabor is a Senior Technical Staff Member at IBM. He has worked in the field of lithography at Arch Chemicals, GlobalFoundries and IBM. This work has included photoresist development, CD control, overlay minimization and 193 dry, immersion and EUV insertion. He received his PhD (1996) in Materials Science and Engineering from Cornell University based on his work on block copolymer photoresists. He is the author of more than 50 journal papers and holder of over 30 patents. He currently serves on the program committee for SPIE Extreme Ultraviolet (EUV) Lithography Conference and is a senior member of SPIE.

1. Development of Current EUV Tools and Future High NA Tools: Abstract:
Development of current EUV tools and future high NA tools: Overview of development that has enabled current 0.33 NA EUV lithography and work needed to enable the high NA EUV lithography to be successfully implemented.

About Anthony Yen

Anthony Yen is Vice President and Head of Technology Development Center at ASML. He received BSEE from Purdue University and SM, EE, PhD, and MBA from MIT. After receiving his doctorate, he worked at Texas Instruments and at IMEC on assignment from TI. From 1997 to 2017, apart from a three-year stint at Cymer (now part of ASML) leading its marketing organization, he was with TSMC where he first led the development of its lithography processes, and then co-led infrastructure development for next-generation-lithography technologies on assignment at SEMATECH; in his last ten years of career at TSMC, he led the development of EUV lithography, including its mask technology, for high-volume manufacturing. Yen is a Fellow of IEEE and SPIE. He is a recipient of the Frits Zernike Award for Microlithography from SPIE and the Outstanding Electrical and Computer Engineer Award from Purdue University. He serves as a Distinguished Lecturer for the IEEE Electron Devices Society.

2. Novel Resists to Achieve Promised High NA EUV Resolution: Abstract:
Novel resists: Novel dry resists have demonstrated industry leading resolution and defectivity. Work is in progress to enable dry resist solutions concurrent with the introduction of high NA EUV. Demonstration of the path to implementation and progress of the materials to enable the full entitlement of the resolution capability of EUV lithography will be presented.

About Rich Wise

Rich Wise is Vice President and General Manager of Dry Resist Product Line at Lam Research. He received his PhD in Chemical Engineering from the University of Houston Plasma Processing Laboratory. Rich led plasma process and equipment development for the International Business Machines corporation memory and logic alliances from 1996 to 2014. He holds over 100 patents in the field of nonequilibrium plasma processing, patterning, and associated semiconductor technologies.

3. EUV and High NA EUV Mask Challenges: Abstract:
EUV and high NA EUV mask challenges: There are numerous issues that become much more difficult with high NA EUV for masks. This includes CD and image placement control where multibeam mask writers, advanced resist processes and improved stitching accuracy management are key. Increased focus on development of new absorbers and on appropriate pattern transfer processes to decrease mask 3D effects is also required.

About Naoya Hayashi

Naoya Hayashi is Honorary Fellow of DNP (Dai Nippon Printing Co., Ltd.) since July, 2022, and had been Research Fellow of DNP prior to that. He received his BS degree in applied chemistry and MS degree in electronic chemistry from Tokyo Institute of Technology, Tokyo, Japan, and joined DNP in 1977. Since then, for about 45 years, he has been responsible for the development of photomask technologies such as electron beam exposure systems, resist materials and processes, phase-shifting materials, and NGL masks for EUV and nanoimprint, at DNP. He became the first Research Fellow of DNP in 2007 and was elected SPIE Fellow in 2011. He was the conference chair of BACUS, SPIE Photomask Technology, in 2015, and received the BACUS Lifetime Achievement Award in 2016. He is author or co-author of 150-plus conference papers and received 10-plus Best Paper Awards from SPIE.

4. High NA EUV Exposure Tool Implications to Chip and Mask Layouts: Abstract:
High NA EUV exposure tool implications: The anamorphic nature of the high NA EUV (4x magnification in X and 8x magnification in Y) results in a field size exactly half that on current EUV and optical tools. When using high NA tools in a semiconductor build that will also use full field tools, there are overlay implications and chip and mask layout issues that need to be optimized.

About Daniel Schmidt

Daniel Schmidt is a Senior Engineer at IBM Research in Albany, NY and leads metrology developments for next generation semiconductor manufacturing. He received his undergraduate degree in Microsystems Technology in Germany and earned a PhD in Electrical Engineering from the University of Nebraska-Lincoln in 2010. After three years of postdoctoral research, he accepted a position as Senior Research Fellow at the National University of Singapore. In 2016, he left academia to start an industry career at GlobalFoundries before joining IBM Research in 2018. Daniel is the author or co-author of 100+ conference papers, 60+ journal articles, and three book chapters. He is a founding member of the Spectroscopic Ellipsometry Technical Group at AVS and serves as a committee member and session chair at SPIE.

5. Resolution Capability and Stitching of Features Across the High NA Exposure Fields: Abstract:
High NA EUV imaging: The resolution for High NA EUV goes down to 20nm pitch and below, enabled by the 0.55NA projection optics featuring a central obscuration. It will be shown how the best imaging performance on wafer can be achieved by doing a careful optimization of the illumination source and mask (stack), balancing image contrast, depth of focus and exposure dose. In addition will be presented how stitching of half fields can be enabled by mask black border and absorber reflectivity control, as well as aerial image crosstalk and double flare maps being included in the OPC flow.

About Eelco van Setten

Eelco van Setten is a Principal Architect at ASML in Veldhoven. He received his MSc in Applied Physics from the University of Twente in the Netherlands in 1999 and joined ASML in 2000. He has worked on the evaluation and understanding of the imaging performance of ASML’s scanners for many generations and technology nodes, covering KrF, ArF, immersion and EUV. Currently he is working as System Engineer for EUV imaging on the development of ASML’s high NA EUV lithography tool with a special interest in EUV resolution enhancement techniques and the impact of the EUV mask stack on imaging performance. He is the author or co-author of 70+ conference papers.