Workshop 2 | Symposia on VLSI Technology and Circuits

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PPAC Analysis and System-Technology Co-Optimization for 3D Memory-on-Logic IC, Many-Core SOC and AI Computing Applications

Organizers: Rongmei Chen (imec) and Geert Van der Plas (imec)

In this workshop, the state-of-the-art of 3D IC technology, design techniques and application will be given. Wafer by wafer and face to face hybrid bonding based fine-pitch (<1µm) 3D interconnects will be reviewed and its application to various 3D IC designs will be introduced. 3D partitioning in various levels of caches for applications ranging from mobile SOC to high performance SOC will be evaluated and traded off for system power, performance, area and cost (PPAC) considering the impact of the 3D interconnect technologies. The purpose of this workshop is to provide a comprehensive view of 3D IC design, PPAC analysis, and optimization from technology, circuit, up to system applications. We will cover various studies related to 3D stacking ranging from high-performance 3D CPU physical design, novel 3D microarchitecture exploration to many-core 3D system design, supported by power delivery and thermal analysis. We will supplement these explorations with hardware measurements from a state-of-the-art 3D demonstrator consisting of a cache coherent interconnect mesh implemented in 3D using sub-10µm 3D pitch and face-to-face hybrid wafer bonding technology on 12nm FinFET process node. 3D opportunities to AI computing will also be discussed.

Live Session: June 13, 7:00 AM-9:00AM (JST)

About Rongmei Chen

Rongmei Chen obtained Bachelor and Ph.D. degrees (with excellent Ph.D. thesis honor) from Tsinghua University, China, in 2012 and 2017 respectively. He was awarded with "Ten Best Progress in Radiation Physics Field of China in 2015-2017" for his innovative contribution to the field of radiation effects of IC. He was a post-doc at LIRMM-CNRS/Montpellier University, France from 2017 to 2019. He joined imec, Leuven, Belgium in 2019. He has been working on 3D IC design and exploration, SRAM design, CNT electronics and IC radiation effects. He is currently a research scientist at imec and is also a Marie Curie scholar. He has published more than 30 papers in journals or conferences including TED, TNS, NSREC, RADECS, IEDM etc. He has served as TPC members for several meetings such as VLSI-SOC, EDTM etc..

About Geert Van der Plas

Geert Van der Plas obtained Ph.D. degree from the Katholieke Universiteit Leuven, Belgium, in 2001. He joined imec, Belgium, in 2003. He has been working on energy efficient data converter, power/signal integrity and 3D integration technologies. Currently he is program manager in the 3D system integration program addressing system scaling using advanced 3D (TSV) and packaging (FO-WLP) technology for high performance, mobile and IoT applications. His interests are in characterization, modeling, system exploration and design enablement of 3D integration technologies.

1. Time Performance Improvement by Agile Design and 3D Integration, Tadahiro Kuroda, The University of Tokyo: Abstract:
With the shift to a knowledge-intensive society, where data replaces materials as resources and value is provided by knowledge-based services instead of things, the IC is changing its role not only as a means to deliver AI processing with increasing sophistication to convert data to knowledge, but also as a key component in building society’s infrastructure in the form of communication networks and base stations. As a result, development time and power performance are emerging as key IC technical challenges. In this presentation, the use of an agile design methodology enabled by high-capacity SRAM and silicon compiler technology, as well as 3D IC integration to improve IC time-performance will be described. Furthermore, cost and performance analysis and comparison with current solutions especially in base station applications will be presented. The target is a 10-fold improvement in both time and performance, in addition to the democratization of IC design.

About Tadahiro Kuroda

Tadahiro Kuroda received the Ph.D. degree in electrical engineering from the University of Tokyo. In 1982, he joined Toshiba Corporation. He was a visiting researcher at the University of California, Berkeley, from 1988 to 1990. He left Toshiba to join Keio University in 2000, and became a full professor in 2002. He was the Mackay Professor at the University of California, Berkeley, in 2007. He has been a professor at The University of Tokyo since 2019. He is the director of System Design Lab (d.lab) and the chairman of RaaS. He is an IEEE Fellow, an IEICE Fellow, and a chair of VLSI Symposia. He has published more than 450+ papers, including 38 ISSCC papers, 29 VLSI Symposia papers, 19 CICC papers and 17 A-SSCC papers. He wrote 30 books/chapters and filed >200 patents.

2. Future of HBM Packaging Technology, Kangwook Lee, SK hynix: Abstract:
The era of IoT (Internet of Things) and IoE (Internet of Everything) is emphasizing the big data analytics and cloud computing. Artificial intelligence, 5G communications and un-tact culture sparked by covid-19 are key driving forces prompting this paradigm shift of our life. The demand on larger capacity and higher bandwidth in the memory products is well aligned with this trend and has been widely implemented for high performance computing (HPC) and server applications, graphic process units and network accelerators, and so on. SK Hynix has been firstly opened up the high bandwidth memory (HBM) market for high performance graphic card in 2014, implementing the innovative packaging technologies such as chip to wafer stack using thermos-compression bonding and non-conductive films, molded wafer handling and testing of multi-die stacked wafer. To adjust the market requirements on HBM, the efforts to increase the capacity and memory bandwidth have being lasted. The number of stack dies increases from 4 in HBM1 to 8 in HBM2/2E and will increase to 12 in HBM3 and 16 in HBM4. Not only die thickness but bond line thickness should be 50~60% lower in 12-high stack than first version of HBM1. Higher capacity is driving new technologies of thin wafer handling process, highly reliable and productive stacking, gap-filling materials and processes. According to the needs of power and bandwidth increase, we are facing with a quite tough challenges in thermal management. Thermal dissipation ability of an HBM cube is a key factor determining product and system performance as the memory bandwidth as well as capacity increases. Thus innovation of packaging material, process, structure and design improvements are necessarily required to meet high thermal dissipation ability. Increasing thermal dummy bumps with adopting highly conductive gap fill material or gap fill fee bond structure such as hybrid bond can be good solutions for lowering thermal resistance. In addition, a variety of possible applications of HBM may lead not only to HBM design and packaging technology improvements but to package component level innovations. Larger interposer size, the adoption of organic substrate or RDL interposer eliminating a silicon interposer, and heterogeneous stack of logic/memory can be another feature for future HBM. In this presentation, we would like to describe several technical achievements during a few years as a leading company of HBM products and introduce future directions to develop key technologies of HBM.

About Kang-Wook Lee

Kang-Wook Lee is currently VP, Head of Package Development at SK Hynix. He received the Ph.D. degree in machine intelligence and systems engineering from Tohoku University, Japan, in 2000. From 2001 to 2002, he was a Postdoctoral Researcher with the Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA. He worked with Memory Division, Samsung Electronics Ltd., Korea, as a Principal Engineer from 2002 to 2008. From 2008 to 2016, he worked with the New Industry Creation Hatchery Center (NICHe), Tohoku University, Japan as a Professor. From 2017 to 2018, he worked with R&D, Amkor Technology Korea, as a VP. He has led the development of 3D TSV packaging for high performance 3D memories (HBM, 3DS), 2.5D/3D heterogeneous integration, hybrid bonding, fan-out wafer-level packaging technologies and 3D TSV reliability studies. He is a Senior Member of IEEE.

3. High-Performance AI Computing and Opportunities for 3D, Mustafa Badaroglu, Qualcomm: Abstract:
We are living in a connected world with access to data in vast amounts relying on energy-efficient performant computation. This has become more challenging under the requirements of seamless interaction between instant data and big data. Instant data generation requires low-power performant devices that can generate the data instantly. Big data requires abundant computing, communication bandwidth, and memory resources to generate the requested service and information. This trend in computing and data movement necessitate a close interaction between memory and computing, particularly for AI applications. In this talk we will describe the sustainability challenges of single-chip AI solutions and shed light to opportunities brought by 2.5D/3D integration for high-performance AI.

About Mustafa Badaroglu

Dr. Mustafa Badaroglu is Principal Engineer and Architect at Qualcomm responsible from technology and architecture development for products employing Compute-In-Memory Technology. Before rejoining Qualcomm, he previously worked at Huawei, Qualcomm, IMEC, ON Semiconductor, and Tubitak Space. During his career he had various assignments for the execution and management of mobile, server, and automotive chipset designs from concept to volume production, process technology pathfinding, electronic design automation, and design-technology co-optimization. Dr. Badaroglu received his Ph.D. in Electrical Engineering and holds a Master of Industrial Management, both from the Catholic University of Leuven. He holds more than 60 published patents and (co)-authored over 100 publications in scientific journals/proceedings. He is the global chair of IRDS More Moore Team focusing on HVM roadmap of logic devices and memory. He is a senior member of IEEE.

4. Architecture, Physical Design and 3D Technology Co-Optimization for Next Generation High Performance Energy Efficient Systems, Brian Cline, Arm: Abstract:
In this talk, we present a compilation of 3D-IC design-related studies done at Arm over the last few years. We begin by discussing the technology landscape around 3D-ICs, including the advanced packaging integration roadmap and the 2D scaling roadmap that it complements. Then we cover the design implications, challenges, and solutions associated with “Macro” level 3D-IC design concepts, as well as higher density, “Micro” level concepts, spanning from 3D partitioning to multi-tier timing and clock design, to power delivery and thermal management. Through this work, we hope to show both the potential benefits afforded by 3D-IC design techniques, but the remaining challenges that still exist, in order to promote a lively workshop discussion on how to create a healthy and robust 3D-IC production ecosystem.

About Brian Cline

Dr. Brian Cline is a Senior Principal Research Engineer in the Devices, Circuits, and Systems research group at Arm, based in Austin, TX. His research interests and responsibilities include the circuit- and system-level design impact of emerging logic devices (primarily post-CMOS), memory devices, next generation lithography (e.g., EUV, DSA, etc.), and next generation integration strategies (e.g., fine-grained 3D bonding, monolithic/sequential 3D, etc.). Dr. Cline also has interests in Electronic Design Automation (EDA) tools and methodologies and Design-Technology Co-optimization (DTCO), mainly with respect to high-speed, power-efficient digital logic design. Dr. Cline received the B.S. degree in electrical engineering from the University of Texas, Austin, in 2004, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 2006 and 2010, respectively. From 2006 to 2010, he was a Graduate Fellow with the Semiconductor Research Corporation (SRC). In 2017, Dr. Cline was chosen as one of the recipients of the SRC Mahboob Khan Outstanding Industry Liaison award. He has co-authored more than 20 patents and 25 papers, including a number of best paper award nominees, invited papers, and plenary sessions.

5. 3D Partitioning Strategies for Memory-on-Logic Designs for Many Core SoCs, Dragomir Milojevic, Universite Libre de Bruxelles: Abstract:
In this presentation we will address the challenges of CMOS scaling for many core SoC designs and propose 3D system integration to address them. Quick overview of different 3D technologies enablers will be presented focusing on their geometrical and electrical properties. Cross section of the stack using IMEC iN3 technology, Face-to-Face hybrid bonding with fine pitch (<1um) and nano-TSVs (0.09um) to escape the stack will be shown. We then cover the 3D Die-by-Die place & route environment and propose methodology for 3D timing optimisation. The above technology assumptions and design flow has been applied for Memory-on-Logic implementation of an open-source, many-core, densely connected system (56 RISCV cores) where all L1 SRAM memory macros have been moved to the top die. Two different partitioning strategies to handle 3D nets with FanOut > 1 will be presented: one where the split occurs on the top die, and the other where the split occurs on the bottom die. Detailed Performance, Power and Area comparison of both 3D partitioning strategies with respect to 2D show significant performance benefits of 3D technology for densely connected SoCs.

About Dragomir Milojevic

Dragomir Milojevic received his master’s and PhD degrees in Electrical Engineering from Ecole polytechnique, Université libre de Bruxelles (ULB), Belgium, where he holds the position of professor in digital electronics and digital systems design. In 2004 he joined IMEC where he first worked on multi-processor and Network-on-Chip architectures for low-power multimedia systems. Since 2008 he is working on system, design and technology co-optimization with advanced nodes, as well as design methodologies & tools for technology aware design of 3D integrated circuits. Dragomir Milojevic authored or co-authored more than 100 journal and conference articles and served as technical program committee member to several conferences in the field

6. Entering a New Dimension with 3D-IC Design, - EDA Perspective, Vinay Patwardhan, CADENCE: Abstract:
With the evolution of advanced packaging technologies and popularity of multi-chiplet flows, EDA tools have to adapt to be more IC centric than PCB centric. There are system design level challenges and traditional ‘planning and implementation’ challenges that have to be mitigated through algorithmic expansion. This presents an opportunity to expand some of Cadence’s powerful planning, implementation and signoff technologies into the 3rd dimension. Cadence’s comprehensive 3D-IC solution to address all the needs of system design, planning and system level signoff analysis will be presented in this session. A couple of examples of new innovative flows for automation of 3D-IC exploration & power-thermal analysis capabilities will be presented.

About Vinay Patwardhan

Vinay Patwardhan has been working at Cadence for over 7 years in different Product Management and Engineering roles focusing on the development of Digital Implementation and signoff products. Prior to Cadence, Vinay has worked at other EDA companies in various Product engineering and Application Engineering roles supporting leading technology innovations. Before moving to EDA, Vinay worked as a physical design engineer, designing high performance SoCs and ASICs at Sun Microsystems and Texas Instruments. Vinay has a Masters degree in Electrical Engineer and Computer Science , from the University of Toledo, Ohio.

7. 3D Technology: The Enabler for Advanced Digital Applications, Francois Andrieu, CEA-Leti: Abstract:
Today, Integrated Circuit roadmap is not only driven by CMOS scaling. 3D technologies are the other key technology booster to improve the Performance Power Area Cost (PPAC) tradeoff at the system level. Especially, 3D enables increasing the data bandwidth and/or the heterogeneous integration and/or the form factor between different sub-circuits. As usual, a universal 3D solution does not exist but there are rather many 3D techniques suited for different applications. For high performance applications, whose performance are limited by the memory access, 3D can bring high data bandwidth by µ-bumps, TSV and active interposer whereas, for compute-bound applications, it can boost the computing performance through a heterogeneous integration of different accelerators. To illustrate this statement, a 220GOPS 96-core processor with 6 Chiplets 3D-stacked on an active interposer offering 0.6ns/mm latency, 3TBit/s/mm2 inter-chiplet interconnects will be highlighted as well as the capability to co-integrate chiplets with bare dice in a multi-chip-module for heterogeneous and scalable high performance compute nodes. For imaging applications driven by the pixel size reduction and the form factor, hybrid bonding (also called Cu bonding) is the straightforward solution. It enables even a sub-µm 3D contact pitch with a wafer to wafer bonding. Finally, in order to increase even further the 3D contact density and to reduce the stack height, the 3D-sequential integration is the ultimate solution. This time, the 3D contact pitch is limited by the lithography alignment between different tiers integrated sequentially on a given wafer. Recent results will be presented, which open the way for high performance transistors and circuits integrated by 3D-sequential techniques. For all of these 3D solutions, the most cost-effective system is obtained with chip/tier specialization and dedicated technology per chip/tier.

About François Andrieu

Dr. François Andrieu is the head of Laboratory “Nano-devices for Memory and Computing” at CEA-Leti, Grenoble, France. He received the M.Sc and Ph.D. degrees from the Grenoble INP, France in 2001 and 2005, respectively. He has been strongly involved in the development of the Fully-Depleted-Silicon-On-Insulator (FDSOI) CMOS technology at Leti and with STMicroelectronics, where he was assigned between 2012-2015 in process-integration and technology-to-design groups. His fields of interest are: advanced CMOS transistors, stacked nanowires, 3D and 3D-sequential integration, RF CMOS, Silicon spin Qbits, NVM Resistive-RAM and In-Memory-Computing. He is currently serving as the 2020/2021 Technical Program Committee Chair of the European Solid-State Device Research Conference (ESSDERC), as well as a TPC member of the VLSI-TSA and SSDM conferences. He is the author or co-author of more than 14 patents, 200 conference abstracts or refereed journal articles, 11 invited papers and 3 book chapters. He received the IEEE senior grade in 2018, the European ERC consolidator grant in 2019 and the IEEE/SEE Brillouin award in 2018.

8. Tackling the Memory Wall via 3D Memory Partitioning : A System Level Perspective, Manu Perumkunnil, imec: Abstract:
For the most advanced CMOS nodes, because of diminished power, performance and cost returns, dimensional scaling must be now complemented by Design and System Technology Co-optimization (DTCO and STCO) strategies, so that SoC bottlenecks can be mitigated. Performance scaling for SoCs has plateaued over the last decade because dimensional technology scaling has not been able to mitigate the ‘Memory Wall’ problem. This problem will only exacerbate with Machine Learning, Artificial Intelligence, Vision, and other data dominated application domains coming to the forefront and also SRAM Power Performance and Area (PPA) gains saturating at advanced nodes. To this end, it has become increasingly clear that 3-D integration and partitioning schemes can offer potential routes to continue scaling and tackle the Memory Wall via DTCO and STCO innovations. This can be via enabling higher integration density, heterogeneous (and novel) technology integration and extending the number of functions per 3-D chip. The 3-D integration scene has attracted a lot of interest over the past decade with demonstrations as well as commercial products like chiplets (AMD Rome, Milan in EPYC products) and 3D stacking (Intel Lakefield) more recently. In this talk, I will give an overview for the need of 3D on-chip cache like memories in highly heterogenous advanced SoCs for the future based on commercial references of today like the Apple A12, Kirin 980 etc via a top-down approach. Following this, based on cross layer exploration and system level simulations, we show that 3D partitioning can help tackle the Memory wall by facilitating large caches and increased bandwidth.

About Manu Perumkunnil

Manu Komalan (M) completed his Integrated Masters in Nanotechnology from Amity University, India in 2011. He received his Ph.D. in Electrical Engineering from Katholieke Univ. Leuven, Belgium and in Computer Science from Universidad Complutense de Madrid in 2017. He then joined imec as a memory system architecture researcher. His research activity primarily involves application dependent exploration, analysis and optimization of Memories across the different layers of abstraction. Currently, he is the Program Manager for the Memory INSITE program at IMEC.