2010 VLSI Circuits Short Course Program Circuit Design for Technology Challenges Tuesday, June 15, Honolulu I Organizers/Chairs: Azeez Bhavnagarwala, IBM TJ Watson Research Koichi Nose, Renesas Electronics Corp. MOS Technology is evolving in its manufacturing, non-silicon materials content and device structure to meet the increasingly severe power drain, performance and cost constraints imposed by emerging wireless and computing platforms in the presence of challenges imposed by variability, leakage and large SoC integration. This Short Course reviews the impact of these trends in MOS technology on circuit design, design methodology and CAD tools used, by providing the design and technology communities a broad exposure to industry-best design practices in Logic, embedded Memory, Analog, SoC Integration, Package, Low Voltage Memory Interface and Memory design that have emerged to meet these Technology challenges. 8:30 a.m. Introduction A. Bhavnagarwala, IBM TJ Watson Research 8:45 a.m. CMOS Technology Trends G. Shahidi, IBM TJ Watson Research 9:45 a.m. CMOS Logic and Embedded Memory Design K. Zhang, Intel 10:45 a.m. Break 11:00 a.m. Design Methodology and Tools in an Evolving CMOS Technology C. Bittlestone, Texas Instruments 12:00 p.m. Lunch 1:00 p.m. Analog/Mixed Signal Design in Digital CMOS D. Fischette, AMD 2:00 p.m. Chip-Package-Co-Design A. Nakamura, Renesas 3:00 p.m. Break 3:15 p.m. Memory Design - Low Power DRAM Circuits and Interface Design - Y. Takai, Elpida Memory Memory Design - Distrubance and Interference Issues in NAND Flash Design - Ki-Tae Park, Samsung 5:15 p.m. Conclusion K. Nose, Renesas Electronics Corp. Frequency Synthesis and Clock Generation Tuesday, June 15, Honolulu II Organizers/Chairs: Andreia Catheliln, STMicroelectronics Shin'ichiro Mutoh, NTT This year the short course on frequency synthesis and clock generation provides exciting presentations from 6 speakers, 3 from industry and 3 from academia. The first two presentations are theoretical ones, treating about basics of jitter and phase noise and then about modeling and simulations techniques of large signal phenomena in PLLs. The other four presentations treat each in detail a specific application field for frequency synthesis or clocking generation: all digital PLLs for wireless, low power frequency synthesis using MEMS/BAW resonators, clocking techniques for high speed wireline and finally PLL design for mm-Wave frequencies. At the end of the presentations, a 30 minutes round table will finally permit to conclude the day. 8:30 a.m. Introduction A. Cathelin, STMicroelectronics 8:45 a.m. Basics of Jitter and Phase Noise A. Abidi, UCLA 9:45 a.m. Modeling/Simulation of Large Signal Phenomena in PLL R. Poore, Agilent EEs of EDA 10:45 a.m. Break 11:00 a.m. Architecture Trends and Requirements for Wireless RF PLLs C-M Hung, Texas Instruments 12:00 p.m. Lunch 1:00 p.m. Low Frequency Synthesis Using BAW/IC B. Otis, University of Washington 2:00 p.m. Clocking Techniques for High-Speed Wireline J-Y Sim, POSTECH 3:00 p.m. Break 3:15 p.m. Mm-Wave PLL Design T. Mitomo, Toshiba Corp. 4:15 p.m. Round Table (all speakers) 5:00 p.m. Conclusion *Breakfast and Coffee are provided.