Shekhar Borkar	Yoshinobu Nakagome
Program Chair	Program Co-Chair

CONFERENCE SCHEDULE

PROGRAM

Joint Rump Session with Technology
RJ1	SOC (System-On-a-Chip) versus SIP (System-In-a-Package)
Organizers	Circuits J. Goodman, Lumic Electronics T. Sakurai, University of Tokyo	Technology D. Buss, Texas Instruments T. Suga, University of Tokyo
Moderator	J. Goodman, Lumic Electronics
In the Internet Age, growth areas for solid-state circuits are in personal internet products (e.g., cell phones, PDAs, Internet audio players, and portable video players/recorders) and the networks used to connect these products (e.g., short distance wireless, DSL modems, cable modems, and eventually fiber to the home and office). These applications all require integration to achieve cost reduction. The panel will explore the question of whether cost reduction will result from SoC integration or SiP integration, or through a new kind of integration called heterogeneous integration.

Session 1		Plenary Session [Tapa II]
Chairpersons		Shekhar Borkar, Intel Corporation Yoshinobu Nakagome, Hitachi, Ltd.
8:30am		Welcome and Opening Remarks
		David Scott, Texas Instruments Masakazu Yamashina, NEC Corp.
8:45am	1.1	The Evolution of Monolithic and Polylithic Interconnect Technology
		James Meindl, Georgia Institute of Technology
9:30am	1.2	Ultra Low-Power CMOS/SOI LSI Design for Future Mobile Systems
		Takakuni Douseki, NTT Telecommunications Energy Laboratories

Session 2		Advanced Interconnect Concepts [Tapa II]
Chairpersons		B. Gieske, AMD M. Mizuno, NEC
10:30am	2.1	Power Dissipation Issues in Interconnect Performance Optimization for Sub-180 nm Designs
Abstract		K. Banerjee and A. Mehrotra*, Stanford University, Stanford, CA and *University of Illinois at Urbana-Champaign, Urbana, IL
10:55am	2.2	A Transition-Encoded Dynamic Bus Technique for High-Performance Interconnects
Abstract		M. Anders, N. Rai, R. Krishnamurthy, S. Borkar, Intel Corporation, Hillsboro, OR
11:20am	2.3	Near Speed-of-Light On-Chip Electrical Inter-connect
Abstract		R. Chang, C. Yue and S. Wong, Stanford University, Stanford, CA
11:45am	2.4	Bending-Comb Capacitor with a Small Parasitic Inductance
Abstract		A. Imamura, M. Fujishima and K. Hoh, The University of Tokyo, Tokyo, Japan

Session 3		Analog Building Blocks for Communications [Tapa III]
Chairpersons		K. Yang, University of California H. Sato, Mitsubishi Electric
10:30am	3.1	Analog Front End IC for 3G WCDMA
Abstract		T.-Y. Chang, X. Jiang, W. Khalil, S. Naqvi, B. Nikjou and J. Tseng, Intel Corporation, Chandler, AZ
10:55am	3.2	A 125 MHz-86 dB IM3 Programmable-Gain Amplifier
Abstract		C.-C. Hsu and J.-T. Wu, National Chiao-Tung University, Hsin-Chu, Taiwan
11:20am	3.3	A Monolithic CMOS 10.4-GHz Phase Locked Loop
Abstract		D.-J. Yang and K.O, University of Florida, Gainesville, FL
11:45am	3.4	An Integrated Mixed-Signal Front-End for Broadband Modems
		I. Mehr. D. Paterson, N. Abaskharoun, J. Lloyd, H. L'Bahy and A. DeSimone, Analog Devices, Inc., Wilmington, MA

Session 4		SRAM and Cache Memories [Tapa II]
Chairpersons		H. Pon, Intel N. Lu, Etron
1:30pm	4.1	Programmable and Automatically-Adjustable Sense-Amplifier Activation Scheme and Multi-Reset Address-Driven Decoding Scheme for High-Speed Reusable SRAM Core
Abstract		T. Suzuki, S. Nakahara, S. Iwahashi, K. Higeta, K. Kanetani, H. Nambu, M. Yoshida* and K. Yamaguchi*, Hitachi Ltd., Tokyo, Japan and *Hitachi ULSI Systems Co., Ltd., Tokyo, Japan
1:55pm	4.2	90% Write Power Saving SRAM Using Sense-Amplifying Memory Cell
		S. Hattori and T. Sakurai, University of Tokyo, Tokyo, Japan
2:20pm	4.3	A 4.5GHz 130nm 32KB L0 Cache with a Self Reverse Bias Scheme
Abstract		S. Hsu, A. Alvandpour, S. Mathew, S.-L. Lu, R. Krishnamurthy and S. Borkar, Intel Corp., Hillsboro, OR
2:45pm	4.4	A 6GHz, 16Kbytes L1 Cache in a 100nm Dual-VT Technology Using a Bitline Leakage Reduction (BLR) Technique
Abstract		Y. Ye, M. Khellah, D. Somasekhar, A. Farhang and V. De, Intel Laboratories, Hillsboro, OR

Session 5		High Speed Serial Links [Tapa III]
Chairpersons		K. Yang, University of California D.K. Jeong, Seoul National University
1:30pm	5.1	An Accurate and Efficient Analysis Method for Multi-Gb/s Chip-to-Chip Signaling Schemes
Abstract		B. Casper, M. Haycock and R. Mooney, Intel Laboratories, Hillsboro, OR
1:55pm	5.2	1.2 Gbps/pin Simultaneous Bidirectional Transceiver Logic with Bit Deskew Technique
Abstract		Y. Fujimura, T. Takahashi, S. Toyoshima, K. Nagashima, J. Baba* and T. Matsumoto*, Hitachi Ltd., Tokyo, Japan and *Hitachi, Ltd., Kanagawa, Japan
2:20pm	5.3	1.5 Gbps, 5150 ppm Spread Spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps Level Detector for Serial ATA
Abstract		M. Sugawara, T. Ishibashi, K. Ogasawara*, M. Aoyama*, M. Zwerg, S. Glowinski, Y. Kameyama, T. Yanagita, M. Fukaishi**, S. Shimoyama, T. Ishibashi and T. Noma, NEC Electronics, Inc., Santa Clara, CA and *NEC Corporation, Kawasaki, Japan and **NEC Corporation, Sagamihara, Japan
2:45pm	5.4	A 0.13-m m CMOS 5-Gb/s 10-meter 28AWG Cable Transceiver with No-Feedback-Loop Continuous-Time Post-Equalizer
Abstract		Y. Kudoh, M. Fukaishi and M. Mizuno, NEC Corporation, Kanagawa, Japan

Session 6		High Speed Bus and SRAM [Tapa II]
Chairpersons		W. Lee, Texas Instruments H. Ikeda, Elpida Memory
3:25pm	6.1	Four-Way Processor 800 MT/s Front Side Bus with Ground Referenced Voltage Source I/O
Abstract		T.P. Thomas and I.A. Young, Intel Corporation, Hillsboro, OR
3:50pm	6.2	Programmable Termination for CML I/O's in High Speed CMOS Transceivers
Abstract		S. Ramaswamy, V. Gupta, P. Landman, B. Parthasarathy, R. Gu, A. Yee, L. Dyson, S. Wu and W. Lee, Texas Instruments, Inc., Dallas, TX
4:15pm	6.3	High Performance SRAMs in 1.5 V, 0.18m m Partially Depleted SOI Technology
		R.V. Joshi, A. Pellela*, O. Wagner*, Y.H. Chan*, W. Dachtera*, S. Wilson* and S.P. Kowalczyk, IBM Research Division, Yorktown Heights, NY and *IBM System 390 Division, Poughkeepsie, NY
4:40pm	6.4	Static Pulsed Bus for On-Chip Interconnects
Abstract		M. Khellah, J. Tschanz, Y. Ye, S. Narendra and V. De, Intel Labs, Hillsboro, OR

Session 7		High Speed (Gb/s) Communications [Tapa III]
Chairpersons		L. McIlrath, R3 Logic Y. Ohtomo, NTT Electronics
3:25pm	7.1	A 5Gbps CMOS Frequency Tolerant Multi Phase Clock Recovery Circuit
Abstract		T. Iwata, T. Hirata, H. Sugimoto, H. Kimura and T. Yoshikawa, Matsushita Electric Industrial Co., Ltd., Osaka, Japan
3:50pm	7.2	A 1.6 Gb/s, 3mW CMOS Receiver for Optical Communication
		A. Emami-Neyestanak, D. Liu, G. Keeler, N. Helman and M. Horowitz, Stanford University, Stanford, CA
4:15pm	7.3	A 0.4-4Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs
		K.-Y.K. Chang, J. Wei, S. Li, Y. Li, K. Donnelly, C. Huang* and S. Sidiropoulos**, Rambus, Inc., Los Altos, CA and *T-RAM, Inc., San Jose, CA and **Aeluros, Inc., Mountain View, CA
4:40pm	7.4	A 1.2Gbps CMOS DFE Receiver with the Extended Sampling Time Window for Application to the SSTL Channel
		Y.-S. Sohn, S.-J. Bae, H.-J. Park and S.-I. Cho*, Pohang University of Science and Technology, Pohang, Korea and *Samsung Electronics Co., Kiheung, Korea

Rump Sessions
Organizers	B. Gieseke, AMD T. Mori, Fujitsu Labs
R-1	Scaling Limit in a Power Limited Environment, Architecture versus Circuit Design
Organizers/Moderators	C.K. Ken Yang, University of California T. Kuroda, Keio University
Panelists	K. Bernstein, IBM C. Hu, TSMC K. Ito, Hitachi A. Kaviani, Xilinx U. Ko, Texas Instruments M. Mizuno, NEC
As technology scaling continues, circuit and system performance may not scale as it has in the past. Increased power dissipation could force technology scaling in new directions leading to new circuit and system architectures. For instance, source/drain and gate leakage for high-performance transistors are increasing with scaled devices. To maintain low leakage, transistor thresholds will not scale linearly with supply impacting transistor performance. This will necessitate both circuit and architectural innovations to employ slower transistors and deliver speed performance without increasing power. This panel discusses what influences technology scaling, and what will maintain continuing performance scaling (if at all possible) circuits or architecture.
R-2	Throw Analog from the Train?
Organizers	K. Nakamura, Analog Devices T. Matsuura, Hitachi
Moderators	K. Nakamura, Analog Devices C. Mangelsdorf, Analog Devices Japan
Panelists	R. Hester, Texas Instruments Q. Huang, Swiss Federal Insitute of Technology T. Matsuura, Hitachi A. Matsuzawa, Matsushita T. Miki, Mitsubishi Electric P. Vorenkamp, Broadcom
Analog has enjoyed virtually a "free ride" on the CMOS migration train behind the digital leaders to successfully improve performance, power, and even cost. In the future, with even deeper sub-micron technologies, this path forward is less clear as analog design is becoming increasingly more difficult in these processes. Low voltage, leaky devices, crummy passives … Is it time to pull the red handle and bring this train to a halt? What do we do to continue our quest for higher performance in CMOS?
R-3	Revolution or Evolution for Memory Technology?
Organizers	H. McAdams, Texas Instruments C. Kim, Samsung
Moderators	B. Prince, Memory Strategies International
Panelists	R. Foss, Atmos K. Kim, Samsung S. Masui, Fujitsu J. Miyamoto, Toshiba R. Salters, Philips Research Labs S. Sweha, Intel S. Tehrani, Motorola
As more applications and appliances target the mobile market, will traditional memories, DRAMs / SRAMs / FLASH, continue to evolve to meet the area, voltage and power reductions required? OR will one or more new, non-volatile technologies, FeRAMs/MRAMs/OUMs, replace them, offering longer battery-life and instant-on capability?

Session 8		Plenary Session II [Tapa II]
Chairpersons		Shekhar Borkar, Intel Corporation Yoshinobu Nakagome, Hitachi, Ltd.
8:30am	8.1	Technology Trends of High-Definition Digital Still Camera System
		Hiroshi Tamayama, Fuji Photo Film Co., Ltd.
9:15am	8.2	Biomedical Implantable Devices
		Ken Wise, University of Michigan

Session 9		High Performance DRAMs [Tapa I]
Chairpersons		H. McAdams, Texas Instruments C. Kim, Samsung Electronics
10:20am	9.1	A 1-Gb/s/pin 512-Mb DDRII SDRAM Using a Digital DLL and a Slew-Rate-Controlled Output Buffer
Abstract		T. Matano, Y. Takai, T. Takahashi, Y. Sakito*, I. Fujii*, Y. Takaishi, H. Fujisawa, S. Kubouchi*, S. Narui, K. Arai*, M. Morino*, M. Nakamura, S. Miyatake*, T. Sekiguchi, K. Koyama and K. Miyazawa, Elpida Memory, Inc., Kanagawa, Japan and *Hitachi ULSI Systems Co., Ltd., Tokyo, Japan
10:45am	9.2	A 110nm 512Mb DDR DRAM with Vertical Transistor Trench Cell
		S. Wuensche, M. Jacunski*, H. Streif, A. Sturm, J. Morrish*, M. Roberge*, M. Clark*, T. Nostrand*, E. Stahl, S. Lewis*, J. Heath, M. Wood*, T. Vogelsang, E. Thoma*, J. Gabric*, M. Kleiner, M. Killian, P. Poechmueller, W. Mueller and G. Bronner*, Infineon Technologies, Essex Junction, VT and *IBM Microelectronics, Essex Junction, VT
11:10am	9.3	A Low-Noise 2-GB/s 256-Mb Packet-Based DRAM with a Robust Array Power Supply
		K.-W. Kwon, B.-S. Moon, C. Kim and S.-I. Cho, Samsung Electronics Co., Ltd., Gyunggi-Do, Korea
11:35am	9.4	1-Gb/s/pin Multi-Gigabit DRAM Design with Low Impedance Hierarchical I/O Architecture
Abstract		H. Fujisawa, T. Takahashi, H. Yoko*, I. Fujii*, Y. Takai and M. Nakamura, Elpida Memory, Inc., Kanagawa, Japan and *Hitachi ULSI Systems Corp., Tokyo, Japan

Session 10		High Speed Microprocessor Techniques [Tapa II]
Chairpersons		B. Gieseke, AMD M. Matsui, Toshiba
10:20am	10.1	SOI-Optimized 64-bit High-Speed CMOS Adder Design
Abstract		J.-J. Kim, R. Joshi*, C.-T. Chuang* and K. Roy, Purdue University, West Lafayette, IN and *IBM T.J. Watson Research Center, Yorktown Heights, NY
10:45am	10.2	A 4GHz 130nm Address Generation Unit with 32-Bit Sparse-Tree Adder Core
Abstract		S. Mathew, M. Anders, R. Krishnamurthy and S. Borkar, Intel Corporation, Hillsboro, OR
10:10am	10.3	Dual Supply Voltage Clocking for 5GHz 130nm Integer Execution Core
Abstract		R. Krishnamurthy, S. Hsu, M. Anders, B. Bloechel, B. Chatterjee*, M. Sachdev* and S. Borkar, Intel Corporation, Hillsboro, OR and *University of Waterloo, Ontario, Canada
11:35am	10.4	Designing a 3GHz, 130nm, IntelÒ PentiumÒ 4 Processor
Abstract		D. Deleganes, J. Douglas, B. Kommandur, M. Patyra, Intel Architecture Group, Hillsboro, OR

Session 11		Analog Techniques [Tapa III]
Chairpersons		K. Nakamura, Analog Devices T. Mori, Fujitsu Labs
10:20am	11.1	A 380-MHz CMOS Linear-in-dB Signal-summing Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems
Abstract		O. Watanabe, S. Otaka, M. Ashida and T. Itakura, Toshiba Corporation, Kawasaki, Japan
10:45am	11.2	A 1-V 3.5-mW CMOS Switched-Opamp Quadrature IF Circuitry for Bluetooth Receivers
Abstract		V.S.-L. Cheung, H.C. Luong and W.-H. Ki, The Hong Kong University of Science and Technology, Kowloon, Hong Kong
11:10am	11.3	A 1.8V Digital A/D Converter in 0.18m m CMOS
Abstract		C.J. Braun and B.H. Engl, Infineon Technologies AG, Munich, Germany
11:35am	11.4	A 16b Quadrature Direct Digital Frequency Synthesizer Using Interpolative Angle Rotation Algorithm
		Y. Song and B. Kim*, Korea Advanced Institute of Science and Technology, Taejon, Korea and *Berkäna Wireless, Inc., San Jose, CA

Session 12		Emerging Memory Architecture and Circuits [Tapa I]
Chairpersons		H. McAdams, Texas Instruments M. Hiraki, Hitachi
1:30pm	12.1	A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory
Abstract		S. Hanzawa, T. Sakata, T. Sekiguchi and H. Matsuoka, Hitachi, Ltd., Tokyo, Japan
1:55pm	12.2	SESO Memory: A CMOS Compatible High Density Embedded Memory Technology for Mobile Applications
Abstract		B. Atwood, T. Ishii, T. Osabe, T. Mine, F. Murai and K. Yano, Hitachi, Ltd., Tokyo, Japan
2:20pm	12.3	MRAM-Writing Circuitry to Compensate for Thermal-Variation of Magnetization-Reversal Current
Abstract		T. Honda, N. Sakimura, T. Sugibayashi, S. Miura, H. Numata, H. Hada and S. Tahara, NEC Corporation, Kanagawa, Japan
2:45pm	12.4	A Low Power 1Mbit MRAM Based on 1T1MTJ Bit Cell Integrated with Copper Interconnects
Abstract		M. Durlam, P. Naji, A. Omair, M. DeHerrera, J. Calder, J. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Williams and S. Tehrani, Motorola Labs, Tempe, AZ

Session 13		SOC and SOP [Tapa II]
Chairpersons		G. Taylor, Intel K. Seno, Sony
1:30pm	13.1	Enabling High-Performance Mixed-Signal System-on-a-Chip (SoC) in High Performance Logic CMOS Technology
Abstract		L.M. Franca-Neto, P. Pardy, M.P. Ly, R. Rangel, S. Suthar, T. Syed, B. Bloechel, S. Lee, C. Burnett, D. Cho, D. Kau, A. Fazio and K. Soumyanath, Intel Laboratories, Hillsboro, OR
1:55pm	13.2	mI/O Architecture for 0.13-mm Wide-Voltage-Range System-on-a-Package (SoP) Designs
Abstract		Y. Kanno, H. Mizuno, N. Oodaira*, Y. Yasu and K. Yanagisawa, Hitachi, Ltd., Tokyo, Japan and *Hitachi ULSI Systems Co., Tokyo, Japan
2:20pm	13.3	0.4-V Logic Library Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array-Voltage Scheme
Abstract		M. Yamaoka, K. Osada and K. Ishibashi, Hitachi, Ltd., Tokyo, Japan
2:45pm	13.4	A 2.9ns Random Access Cycle Embedded DRAM with a Destructive-Read Architecture
		C.-L. Hwang, T. Kirihata, M. Wordeman, J. Fifield*, D. Storaska, D. Pontius*, G. Fredeman, B. Ji, S. Tomashot* and S. Dhong**, IBM Microelectronics, Hopewell Junction, NY, and *IBM Micro-electronics, Essex Jucntion, VT and **IBM Microelectronics, Austin, TX

Session 14		Low-Power RF & Building Blocks [Tapa III]
Chairpersons		A. Abidi, University of California D.K. Jeong, Seoul National University
1:30pm	14.1	A Low Power 200MHz Receiver for Wireless Hearing Aid Devices
Abstract		A. Deiss and Q. Huang, Swiss Federal Institute of Technology, Zürich, Switzerland
1:55pm	14.2	A 6.5GHz CMOS FSK Modulator for Wireless Sensor Applications
Abstract		S.H. Cho and A.P. Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA
2:20pm	14.3	A 40 GHz VCO with 9 to 15% Tuning Range in 0.13m m SOI CMOS
Abstract		N. Fong, J.-O. Plouchart*, N. Zamdmer**, D. Liu*, L. Wagner**, C. Plett and G. Tarr, Carleton University, Ottawa, Ontario, Canada and *IBM T.J. Watson Research Center, Yorktown Heights, NY and **IBM SRDC, Hopewell Junction, NY
2:45pm	14.4	A 1-V 2.5-mW 5.2-GHz Frequency Divider in a 0.35-mm CMOS Process
		J.M.C. Wong, V.S.L. Cheung and H.C. Luong, Hong Kong University of Science and Technology, Kowloon, Hong Kong

Session 15		Design for Emerging Technologies [Tapa I]
Chairpersons		S. Kosonocky, IBM K. Kotani, Tohoku University
3:25pm	15.1	Ferroelectric-Based Functional Pass-Gate for Low-Power VLSI
Abstract		H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori*, T. Nakamura* and H. Takasu*, Tohoku University, Sendai, Japan and *Rohm Co., Ltd., Kyoto, Japan
3:50pm	15.2	Ferroelectric Memory Based Secure Dynamically Programmable Gate Array
Abstract		S. Masui, T. Ninomiya*, M. Oura, W. Yokozeki*, K. Mukaida* and S. Kawashima, Fujitsu Laboratories Limited, Tokyo, Japan and *Fujitsu Limited, Tokyo, Japan
4:15pm	15.3	Selective Node Engineering for Chip-Level Soft Error Rate Improvement
Abstract		T. Karnik, S. Vangal, V. Veeramachaneni, P. Hazucha, V. Erraguntla and S. Borkar, Intel Laboratories, Hillsboro, OR
4:40pm	15.4	Threshold-voltage Balance for Minimum Supply Operation
Abstract		G. Ono and M. Miyazaki, Hitachi, Ltd., Tokyo, Japan

Session 16		Digital System Optimization Techniques [Tapa II]
Chairpersons		P. Larsson-Edefors, Chalmers University of Technology M. Nagata, Hiroshima University
3:25pm	16.1	Crosstalk Delay Analysis of a 0.13-m m-Node Test Chip and Precise Gate-Level Simulation Technology
Abstract		Y. Sasaki, M. Satoh*, M. Kuramoto*, F. Kikuchi*, T. Kawashima*, H. Masuda** and K. Yano, Hitachi, Ltd., Tokyo, Japan and *Hitachi ULSI Systems Co., Ltd., Tokyo, Japan and **STARC, Kanagawa, Japan
3:50pm	16.2	Design Rule for Frequency-Voltage Cooperative Power Control and Its Application to an MPEG-4 Decoder
Abstract		K. Aisaka, T. Aritsuka, S. Misaka, K. Toyama, K. Uchiyama, K. Ishibashi, H. Kawaguchi* and T. Sakurai*, Hitachi, Ltd., Tokyo, Japan and *University of Tokyo, Tokyo, Japan
4:15pm	16.3	Design Optimizations of a High Performance Microprocessor Using Combinations of Dual-VT Allocation and Transistor Sizing
Abstract		J. Tschanz, Y. Ye, L. Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar and V. De, Intel Labs, Hillsboro, OR
4:40pm	16.4	Design & Validation of the PentiumÒ III and PentiumÒ 4 Processors Power Delivery
Abstract		T. Rahal-Arabi, G. Taylor, M. Ma and C. Webb, Intel Corporation, Hillsboro, OR

Session 17		Wireless Transceivers [Tapa III]
Chairpersons		K. Nakamura, Analog Devices H. Sato, Mitsubishi Electric
3:25pm	17.1	A 2.17 dB NF, 5GHz Band Monolithic CMOS LNA with 10 mW DC Power Consumption
Abstract		H.-W. Chiu and S.-S. Lu, National Taiwan University, Taipei, Taiwan, R.O.C.
3:50pm	17.2	A 1.8-V Operation RFCMOS Transceiver for Bluetooth
Abstract		H. Komurasaki, T. Heima, T. Miwa, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T. Sano, H. Sato, T. Miki and N. Kato, Mitsubishi Electric Corporation, Hyogo, Japan
4:15pm	17.3	A 17mW Transmitter and Frequency Synthesizer for 900MHz GSM Fully Integrated in 0.35-m m CMOS
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