2001 SYMPOSIUM ON VLSI CIRCUITS

Welcome to the 2001 Symposium on VLSI Circuits


You are cordially invited to attend the 2001 Symposium on VLSI Circuits, to be held on June 14-16th 2001, at the Rihga Royal Hotel Kyoto in Kyoto, Japan.

The Symposium will celebrate its fifteenth anniversary, establishing as a major international forum for presenting and exchanging ideas on important and exciting new developments in the VLSI circuit design. This is the first symposium in the twenty first century, and we have expanded the scope to include new concepts in LSI and physical design tools, in addition to the traditional Analog, Digital, Memory, Signal Processing and Communications circuits. Contributions to the Symposium come from both: industry and academia around the world. Preceding the Symposium on June 13th, a one-day Short Course on VLSI circuits will be held. This short course will focus on "Physical Design for Low-power and High-performance Microprocessor Circuits". Six speakers will talk about their advanced design techniques for processors. Following the tradition of the last several years, the Symposium on VLSI Circuits will be held for three days following the Symposium on VLSI Technology at the same location.

This year, the program committee reviewed 153 papers, and selected 76 papers for presentation. These papers disclose new and interesting circuit design concepts for memories, processors, communication circuits, analog, and signal processing. We certainly hope that the technical content of the program will make the Symposium a fruitful and enjoyable event for all the attendees.

We have also invited four distinguished speakers to describe recent advances and new challenges in VLSI circuits and technology; vision chips, flat panel displays for mobile applications, physics-based device models, and digital light projectors.

To complement the formal talks, we have arranged four evening rump sessions on interesting and provocative subjects to give you an opportunity to participate in the discussions with international participants. The rump session topics cover RF Circuits and Technologies, Start-ups and Big companies, Power supply circuits, and DRAM architectures.

This web site contains the advance program together with forms for the Symposium registration and hotel reservations. Please try to complete and return these forms as soon as possible. Although the on-site registration will be available at the conference, pre-registration will facilitate Symposium planning.

We look forward to meeting with you at the Symposium in Kyoto.



Masakazu Yamashina

Shekhar Borkar
Program Chair Program Co-Chair




CONFERENCE SCHEDULE


Tuesday, June 12

8:00-17:00

Registration
Wednesday, June 13 7:00 Breakfast [Suzaku]
8:00 Registration
9:30-11:55 Short Course [Suzaku]
13:15-16:35 Short Course [Suzaku]
18:00-20:00 Reception [Suzaku]
20:00-22:00 Technology and Circuits Joint Rump Session [Suzaku]
Thursday, June 14 7:00 Breakfast [Suzaku]
8:00 Registration
8:30-10:15 Session 1 Welcome and Plenary Session I [Suzaku]
10:35 Session 2 RF Front End I [Suzaku]
13:45-15:25 Session 3 High Speed Circuits [Suzaku I]
Session 4 High Performance DRAM [Suzaku II]
Session 5 PLLs and Frequency Synthesizers [Suzaku III]
15:45-17:25 Session 6 Design Optimizations and New Technologies [Suzaku I]
Session 7 Memory Redundancy [Suzaku II]
Session 8 Variable Gain Amplifiers [Suzaku III]
20:00-22:00 Rump Sessions [Suzaku I,II,III]
Friday, June 15 7:00 Breakfast [Suzaku]
8:30-10:00 Session 9 Plenary Session II [Shunju]
10:20-12:00 Session 10 Multimedia and Networking [Shunju]
13:30-15:10 Session 11 RF VCOs [Shunju I]
Session 12 Nonvolatile Memories [Shunju II]
Session 13 Voltage and Current Generation [Shunju III]
15:30-17:10 Session 14 Data Transmission [Shunju I]
Session 15 Emerging Technology [Shunju II]
Session 16 Sensor and Filters [Shunju III]
18:00-20:00 Dinner [Suzaku]
Saturday, June 16 7:00 Breakfast [Suzaku]
8:30-10:10 Session 17 Clock Distributions and Bus Drivers [Shunju I]
Session 18 Passive Elements and Test [Shunju II]
Session 19 ADC and Track/Hold [Shunju III]
10:30-12:10 Session 20 Low Power Design [Shunju I]
Session 21 Embedded RAMs [Shunju II]
Session 22 RF Front End II [Shunju III]




PROGRAM


Wedensday, June 13
20:00-22:00

Joint Rump Session with Technology

J-R

Which Features of an IC Technology will Benefit Radio SOC?
Moderators   H. Iwai,   Tokyo Inst. of Tech.
  S. Shichijo,   TI
  M. Hotta,   Hitachi
  A. Abidi,   UCLA

Panelists

  A. Matsuzawa,   Matsushita Electric
  H. Sato,   Mitsubishi Electric
  S.-C. Wong,   TSMC
  F. Behbahani,   Valence Semiconductor
  E. MacRobbie,   Conexant Systems
  R. Rofougaran,   Broadcom
Integration of radio and digital functions on a single chip beyond todays cellular prototypes will enable a new generation of radio devices with potentially very large markets. To meet the targets of low cost and low power, what are reasonable levels of integration? What are the most important IC technology attributes to enable this: transistor fT, density, on-chip passives, substrate isolation, etc.? Which one mainstream technology best embodies these features?
back to conference schedule


Thursday, June 14

Session 1

Welcome and Plenary Session [Suzaku]
Chairpersons M. Yamashina, NEC
S. Borkar, Intel

8:30

1-1
Welcome and Opening Remarks
   T. Sakurai, D. Scott
Univ. of Tokyo, Texas Instruments

8:45

1-2
Digital Vision Chips and High-Speed Vision Systems (Invited)
   M. Ishikawa and T. Komuro
University of Tokyo

9:30

1-3
Physics-Based Device Model for Circuit Simulation-BSIM (Invited)
   C. Hu
UC Berkley
back to conference schedule
(Break 10:15-10:35)
Thursday, June 14

Session 2

RF Front End I [Suzaku]
Chairpersons T. Mori, Fujitsu Labs.
G. Nasserbakht, Proxim

10:35

2-1
Full-CMOS 2.4GHz Wideband CDMA Transmitter and Receiver with Direct Conversion Mixers and DC-Offset Cancellation
Abstract K.-Y. Lee, S.-W. Lee, Y. Koo, H.-K. Huh, H.-Y. Nam, J.-W. Lee*, J. Park*, K. Lee*,
D.-K. Jeong and W. Kim
Seoul National University, Korea and *Global Communication Technology, Inc., USA

11:00

2-2
Single-Chip IF Transceiver IC with Wide Dynamic Range Variable Gain Amplifiers for Wideband CDMA Applications
Abstract T. Maruyama, K. Kaneki, K. Takahashi, H. Sato, T. Iga and N. Kato
Mitsubishi Electric Corporation, Japan

11:25

2-3
A 0dB-IL, 2140±30 MHz Bandpass Filter Utilizing Q-Enhanced Spiral Inductors in Standard CMOS
Abstract T. Soorapanth and S.S. Wong
Stanford University, USA

11:50

2-4
A 2 GHz Merged CMOS LNA and Mixer for WCDMA
Abstract A. Karimi-Sanjaani, H. Sjoland* and A.A. Abidi
University of California, USA and *Lund University, Sweden
back to conference schedule
(Lunch 12:15-13:45)
Thursday, June 14

Session 3

High Speed Circuits [Suzaku I]
Chairpersons M. Motomura, NEC
J. Goodman, Chrysalis-ITS

13:45

3-1
Robustness of sub-70nm Dynamic Circuits: Analytical Techniques and Scaling Trends
Abstract M. Anders, R. Krishnamurthy, R. Spotten* and K. Soumyanath
Intel Corporation, USA and *Intel Corporation, Israel

14:10

3-2
A 0.13 mm 6GHz 256x32b Leakage-tolerant Register File
Abstract R. Krishnamurthy, A. Alvandpour, G. Balamurugan*, N. Shanbhag*, K. Soumyanath and S. Borkar
Intel Corporation and *University of Illinois at Urbana-Champaign, USA

14:35

3-3
480ps 64-bit Race Logic Adder
Abstract S.-J. Lee, R. Woo and H.-J. Yoo
Korea Advanced Institute of Science and Technology, Korea

15:00

3-4
A Conditional Keeper Technique for Sub-0.13m Wide Dynamic Gates
Abstract A. Alvandpour, R. Krishnamurthy, K. Soumyanath and S. Borkar
Intel Corporation, U.S.A.
back to conference schedule
(Break 15:25-15:45)
Thursday, June 14

Session 4

High Performance DRAM [Suzaku II]
Chairpersons C. Kim, Samsung Electronics
H. Pon, Intel

13:45

4-1
A Cell Transistor Scalable Array Architecture for High-Density DRAMs
Abstract D. Takashima and H. Nakano
TOSHIBA Corporation, JAPAN

14:10

4-2
Bit Line Coupling Scheme and Electrical Fuse Circuit For Reliable Operation of High Density DRAM
Abstract K. Lim, S. Kang, J. Choi, J. Joo, Y. Lee, J. Lee, S. Cho and B. Ryu
Samsung, Korea

14:35

4-3
An Area-Efficient 2GB/s 256Mb Packet-based DRAM with Daisy-Chained Redundancy Scheme
Abstract B-S. Moon, J-W. Chai, J-S. Kim, S-M. Yim, S-A. Kim, C. Kim and S-I. Cho
Samsung Electronics, Korea

15:00

4-4
A 66-400 MHz, Adaptive-Lock-Mode DLL Circuit with Duty-Cycle Error Correction
Abstract Y. Okuda, M. Horiguchi and Y. Nakagome
Hitachi, Ltd., Japan
back to conference schedule
(Break 15:25-15:45)
Thursday, June 14

Session 5

PLLs and Frequency Synthesizers [Suzaku III]
Chairpersons T. Kamei, Oki Electric
G. Nasserbakht, Proxim

13:45

5-1
A Stabilization Technique for Phase-Locked Frequency Synthesizers
Abstract T.-C. Lee and B. Razavi
University of California, USA

14:10

5-2
A Fully-Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems
Abstract Y. Koo, H. Huh, Y. Cho, J. Lee*, J. Park*, K. Lee*, D.-K. Jeong and W. Kim
Seoul National University, Korea and *Global Communication Technology, Inc., USA

14:35

5-3
1-GHz and 2.8-GHz CMOS Injection-locked Ring Oscillator Prescalers
Abstract R.J. Betancourt-Zamora, S. Verma and T.H. Lee
Stanford University, USA

15:00

5-4
Automatic Calibration of Modulated S - D Frequency Synthesizers
Abstract D.R. McMahill and C.G. Sodini
Massachusetts Institute of Technology, USA
back to conference schedule
(Break 15:25-15:45)
Thursday, June 14

Session 6

Design Optimizations and New Technologies [Suzaku I]
Chairpersons H. Kabuo, Matsushita Electric
S. Borkar, Intel

15:45

6-1
Autonomous-Decentralized Low-power System LSI Using Self-Instructing Predictive Shutdown Method
Abstract T. Shimizu, F. Arakawa and T. Kawahara
Hitachi, Ltd., Japan

16:10

6-2
ASIC Design Methodology with On-Demand Library Generation
Abstract H. Onodera, M. Hashimoto and T. Hashimoto
Kyoto University, Japan

16:35

6-3
Scaling trends of Cosmic Rays induced Soft Errors in static latches beyond 0.18m
Abstract T. Karnik, B. Bloechel, K. Soumyanath, V. De and S. Borkar
Intel Corporation, USA

17:00

6-4
Single-Electron Pass-Transistor Logic and its Application to a Binary Adder
Abstract Y. Ono and Y. Takahashi
NTT Basic Research Laboratories, Japan
back to conference schedule
Thursday, June 14

Session 7

Memory Redundancy [Suzaku II]
Chairpersons M. Hiraki, Hitachi
D. Scott, Texas Instruments

15:45

7-1
A Post-Package Bit-Repair Scheme Using Static Latches with Bipolar-Voltage Programmable Antifuse Circuit for High-Density DRAMs
Abstract K.-S. Min, J.-T. Park, S.-P. Lee, Y.-H. Kim, T.-H. Yang, J.-D. Joo, K.-M. Lee, J.-K. Wee and J.-Y. Chung
Hyundai Electronics Industries Co. Ltd., Korea

16:10

7-2
A New Column Redundancy Schene for Yield Improvement of High Speed DRAMs with Multiple Bit Pre-fetch Structure
Abstract J.-G. Lee, Y.-H. Jun, K.-H. Kyung, C. Yoo, Y.-H. Cho and S.-I. Cho
Samsung Electronics Co., Ltd., Korea

16:35

7-3
A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit
Abstract M. Yamaoka, K. Yanagisawa, S. Shukuri, K. Norisue* and K. Ishibashi
Hitachi, Ltd. and *Hitachi ULSI Systems Co., Ltd., Japan
back to conference schedule
Thursday, June 14

Session 8

Variable Gain Amplifiers [Suzaku III]
Chairpersons A. Wada, Sanyo Electric
K. Azadet, Agere Systems

15:45

8-1
A 50-MHz 98-dB Dynamic-Range dB-Linear Programmable-Gain Amplifier with 2-dB Gain Steps for 3-V Power Supply
Abstract K. Nah and B. Park
Samsung Electronics Co., Ltd., Korea

16:10

8-2
A Temperature Stable CMOS Variable Gain Amplifier with 80-dB Linearly Controlled Gain Range
Abstract T. Yamaji, N. Kanou and T. Itakura
Toshiba Corporation, Japan

16:35

8-3
A Variable Gain IF Amplifier with -67dBc IM3-Distortion at 1.4Vpp Output in 0.25mm CMOS
Abstract K. Philips and E.C. Dijkmans
Philips Research Laboratories, The Netherlands
back to conference schedule
Thursday, June 14
20:00-22:00

Rump Sessions

Organizers
M. Hiraki, Hitachi
B. Gieseke, AMD
R-1 Will Start-Ups Outperform Big Companies?

Organizers/Moderators
  K. Azadet,   Agere Systems
  N. Lu,   Etron

Panelists
  M. Fukuma,   NEC
  T. Iizuka,   THine Electronics
  G. Kano,   Kochi Univ. of Technol.
  S. Kohyama,   Toshiba
  B. Ackland,   Agere Systems
  V.G. Oklobdzija,   Integration
  C. Sodini,   MIT
Start-ups are more agile, more focused, often have higher growth potential in the stock market than large companies. They are more competitive in recruiting, their equity can be a very lucrative source of revenue for employees. They can afford to fail and therefore can afford taking high risk.
On the other hand, big companies are more solid and less susceptible to stock market fluctuations, they can own and evelop new sophisticated technology, they are more diversified and have more stable revenue growth. They have well-developed sales channels, better capacity in large-scale manufacturing, more loyal employees.
As they grow, start-ups acquire smaller companies, while big companies spin-off to become smaller. Which is the best model in the new millennium?

R-2
Power Supply for Future System LSIs

Organizers
  S. Kosonocky,   IBM
  T. Kuroda,   Keio University

Moderators
  S. Kosonocky,   IBM
  M. Matsui,   Toshiba

Panelists
  M. Hamada,   Toshiba
  H. Mizuno,   Hitachi
  S. Sakiyama,   Matsushita Electric
  L. Clark,   Intel
  B.K. Kates,   AMD
  D. Stout,   IBM
System integration is increasing rapidly in deep submicron designs, along with power dissipation. While voltage scaling is the most useful lever in decreasing active power in many circuits, but the power supply cannot scale as fast for some circuits. Constraints in d.c. power, analog circuits and memory circuits will force different optimal power supply levels for these circuits. Novel approaches in distribution and management of these supplies is necessary to optimize chip area, performance and power dissipation. How much dynamic power management will be necessary for these future devices ? Will power management limit what can be efficiently integrated on a single chip?

R-3
Diverse DRAM Architectures: Why and Who Wins?
Organizers   H. Pon,   Intel
  M. Motomura,   NEC
Moderators   B. Martino,   Motorola

Panelists
  H. Ikeda,   Elpida Memory
  C. Kim,   Samsung Electronics
  T. Sugiura,   Advantest
  M. Taguchi,   Fujitsu
  J. Halbert,   Intel
  S. Polzin,   AMD
Today, several DRAM architectures are available such as rambus DRAM, DDR-SDRAM, FCRAM, VC-DRAM, etc., and many arguing factors are discussed for the trade-off between cost and performance. This issue will be different from several various application areas broadening from high-end server to desktop PC, and consumer markets. So, we want to discuss which DRAM architecture will be the best for increasing the system performance while having low cost to fit many purposes.
back to conference schedule
Friday, June 15

Session 9

Plenary Session II [Shunju]
Chairpersons M. Yamashina, NEC
S. Borkar, Intel

8:30

9-1
Development Trend of LTPS TFT LCD for Mobile Applications (Invited)
Abstract K. Yoneda
SANYO Electric

8:30

9-2
Digital Light Projectors (Invited)
Abstract P. VanKessel
Texas Instruments
back to conference schedule
(Break 10:00-10:20)
Friday, June 15

Session 10

Multimedia and Networking [Shunju]
Chairpersons M. Matsui, Toshiba
C.-T. Chuang, IBM T.J. Watson Research Ctr.

10:20

10-1
A 120mW Embedded 3D Graphics Rendering Engine with 6Mb Logically Local Frame-Buffer and 3.2GByte/s Run-time Reconfigurable Bus for PDA-Chip
Abstract R. Woo, C.-W. Yoon, J. Kook, S.-J. Lee, K. Lee, Y.-H. Park and H.-J. Yoo
Korea Advanced Institute of Science and Technology, Korea

10:45

10-2
Low Power Motion Compensation Block IP with embedded DRAM Macro for Portable Multimedia Applications
Abstract C.-W. Yoon, J. Kook, R. Woo, S.-J. Lee, K. Lee and H.-J. Yoo
KAIST, Korea

10:10

10-3
Dynamically Reconfigurable Logic LSI - PCA-1
Abstract H. Ito, R. Konishi, H. Nakada, K. Oguri*, A. Nagoya, N. Imlig, K. Nagami, T. Shiozawa and M. Inamori
NTT Network Innovation Laboratories and *Nagasaki University, Japan

11:35

10-4
A 1GHz Power Efficient Single Chip Multiprocessor System For Broadband Networking Applications
Abstract S. Santhanam, R. Allmon, R. Blake, N. Bunger, B. Campbell, M. Carlson, Z. Chen, J. Cheng, T. Do, D. Dobberpuhl, J. Ingino, D. Kidd, D. Kruckemyer, J. Lee, D. Murray, S. Nishimoto, L. O'Donnell, M. Oykher, M. Panich, M. Pearce, D. Priore, R. Rogermoser, D. Suh, V. Sundaresan, E. Supnet, V.V. Kaenel, G. Yee and C. Vo
Broadcom Corporation, USA
back to conference schedule
(Lunch 12:00-13:30)
Friday, June 15

Session 11

RF VCOs [Shunju I]
Chairpersons D.-K. Jeong, Seoul National Univ.
L.D. McIlrath, MIT

13:30

11-1
A 1.57 GHz Fully integrated Very Low Phase Noise Quadrature VCO
Abstract P. Vancorenland and M. Steyaert
ESAT-MICAS, Belgium

13:55

11-2
An optimally coupled 5 GHz quadrature LC oscillator
Abstract P. van de Ven, J. van der Tang*, D. Kasperkovitz and A. van Roermund*
Philips Research Laboratories and *Eindhoven University of Technology, The Netherlands

14:20

11-3
A Highly-Tunable 12 GHz Quadrature LC-VCO in SiGE BiCMOS Process
Abstract A.L. Coban, K. Ahmed and C. Chang
Conexant Systems, Inc., USA

14:45

11-4
A 1.8 GHz CMOS VCO with Reduced Phase Noise
Abstract P. Andreani and H. Sjoland
Lund University, Sweden
back to conference schedule
(Break 15:10-15:30)
Friday, June 15

Session 12

Nonvolatile Memories [Shunju II]
Chairpersons K. Kotani, Tohoku Univ.
J. Bowles, AMD

13:30

12-1
A Novel Sensing Scheme for a MRAM with a 5% MR Ratio
Abstract K. Yamada, N. Sakai, Y. Ishizuka and K. Mameno
SANYO Electric Co., LTD., Japan

13:55

12-2
A Pulse-Tuned Charge Controlling Scheme for Uniform Main and Reference Bitline Voltage Generation on 1T1C FeRAM
Abstract H.-B. Kang, H.-W. Kye, D.-J. Kim, G.-I. Lee, J.-H. Park, J.-K. Wee, S.-S. Lee, S.-K. Hong, N.-S. Kang and J.-Y. Chung
Hyundai Electronics, Korea

14:20

12-3
A Bit-Line GND Sense Technique for Low-Voltage Operation FeRAM
Abstract S. Kawashima, T. Endo, A. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita and M. Aoki
Fujitsu Laboratories Limited, JAPAN

14:45

12-4
A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM
Abstract T. Miwa, J. Yamada, H. Koike, T. Nakura, S. Kobayashi, N. Kasai and H. Toyoshima
NEC Corporation, Japan
back to conference schedule
(Break 15:10-15:30)
Friday, June 15

Session 13

Voltage and Current Generation [Shunju III]
Chairpersons Y. Ohtomo, NTT
S. Kosonocky, IBM, T.J. Watson Research Center

13:30

12-1
An Efficient Digital Sliding Controller for Adaptive Power Supply Regulation
Abstract J. Kim and M. Horowitz
Stanford University, USA

13:55

13-2
A 1.8V Single-Inductor Dual-Output Switching Converter for Power Reduction Techniques
Abstract D. Ma, W.-H. Ki, C.-Y. Tsuj and P.K.T. Mok
The Hong Kong University of Science and Technology, China

14:20

13-3
A 0.6-V Voltage Reference Circuit Based on S-VTH Architecture in CMOS/SIMOX
Abstract M. Ugajin and T. Tsukahara
NTT Telecommunications Energy Laboratories, Japan

14:45

13-4
Sub-1 V Process-Compensated MOS Current Generation Without Voltage Reference
Abstract S. Narendra, D. Klowden and V. De
Intel Corporation, USA
back to conference schedule
(Break 15:10-15:30)
Friday, June 15

Session 14

Data Transmission [Shunju I]
Chairpersons Y. Ohtomo, NTT
A. Abidi, Univ. of California

15:30

14-1
A Single-Chip 12.5Gbaud Transceiver for Serial Data Communication
Abstract D. Friedman, M. Meghelli, B. Parker, J. Yang, H. Ainspan and M. Soyuer
IBM T.J. Watson Research Center, USA

15:30

14-2
An 84-mW 4-Gb/s Clock and Data Recovery Circuit for Serial Link Applications
Abstract M.-J.E. Lee, W.J. Dally, J.W. Poulton*, P. Chiang and S.F. Greenwood
Stanford University and *UNC at Chapel Hill, USA

16:20

14-3
An SOI CMOS LVDS Driver and Receiver Pair
Abstract B. Young
Motorola, USA

16:45

14-4
A 15-GHz Wireless Interconnect Implemented in a 0.18-mm CMOS Technology Using Integrated Transmitters, Receivers, and Antennas
Abstract B.A. Floyd, C.-M. Hung and K.K. O
University of Florida, USA
back to conference schedule
(Dinner 18:00-20:00)
Friday, June 15

Session 15

Emerging Technology [Shunju II]
Chairpersons M. Hiraki, Hitachi
B. Gieseke, AMD

15:30

15-1
Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits
Abstract M. Nagata, T. Ohmoto, Y. Murasaka, T. Morie and A. Iwata
Hiroshima University, Japan

15:55

15-2
Parametric Yield Enhancement System via Circuit Level Device Optimization using Statistical Circuit Simulation
Abstract M. Miyama, S. Kamohara, K. Okuyama and Y. Oji
Hitachi, Ltd., Japan

16:20

15-3
A Floating-Body Charge Monitor Circuit for Partially Depleted SOI CMOS
Abstract J.B. Kuang, M.J. Saccamango and S. Ratanaphanyarat
back to conference schedule
(Dinner 18:00-20:00)
Friday, June 15

Session 16

Sensor and Filters [Shunju III]
Chairpersons A. Hyogo, Science Univ. of Tokyo
L.D. McIlrath, MIT

15:30

16-1
A Pixel-Level Automatic Calibration Circuit Scheme for Sensing Initialization of a Capacitive Fingerprint Sensor LSI
Abstract H. Morimura, S. Shigematsu, T. Shimamura*, K. Machida* and H. Kyuragi*
NTT Lifestyle and Environmental Technology Laboratories and *NTT Telecommunications Energy Laboratories, Japan

15:55

16-2
A 200MHz 7th-order Equiripple Continuous-Time Filter by design of nonlinearity suppression in 0.25mm CMOS Process
Abstract T. Morie, H. Fujiyama and S. Dosho
Matsushita Electric Industrial Co., Ltd, Japan

16:20

16-3
A Micropower Log-Domain Filter Using Enhanced Lateral PNPs in a 0.25mm CMOS Process
Abstract N. Krishnapura and Y. Tsividis*
Celight Inc. and *Columbia University, USA.
back to conference schedule
(Dinner 18:00-20:00)
Saturday, June 16

Session 17

Clock Distributions and Bus Drivers [Shunju I]
Chairpersons K. Kobayashi, Kyoto Univ.
G. Taylor, Intel

8:30

17-1
A Low-Swing Clock Double-Edge Triggered Flip-Flop
Abstract C. Kim and S.-M. Kang
University of Illinois at Urbana-Champaign, USA

8:55

17-2
On-die Clock Jitter Detector for High Speed Microprocessors
Abstract R. Kuppuswamy, K. Callahan, K. Wong, D. Ratchen and G. Taylor
Intel Corp., USA

9:20

17-3
P-boosted Source Followers: A Robust Energy-efficient Bus Driver Technique
Abstract R. Krishnamurthy, K. Soumyanath and D. Ayers
Intel Corporation, USA

9:45

17-4
Two schemes to reduce interconnect delay in bi-directional and uni-directional buses
Abstract K. Nose and T. Sakurai
University of Tokyo, Japan
back to conference schedule
(Break 10:10-10:30)
Saturday, June 16

Session 18

Passive Elements and Test [Shunju II]
Chairpersons M. Motomura, NEC
K. Azadet, Agere Systems

8:30

18-1
Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
Abstract K. Banerjee and A. Mehrotra*
Stanford University and *University of Illinois at Urbana-Champaign, USA

8:55

18-2
Silicon Integrated High Performance Inductors in a 0.18mm CMOS Technology for MMIC
Abstract H.-M. Hsu, J.-G. Su*, S.-C. Wong, Y.-C. Sun, C.-Y. Chang*, T.-Y.Huang*, C.C. Tsai, C.H. Lin, R.S. Liou, R.Y. Chang, T.H. Yeh, C.H. Chen, C.F. Huang, H.D. Huang and C.W. Chen
Taiwan Semiconductor Manufacturing Co., and *National Chiao-Tung University, Taiwan, R.O.C.

9:20

18-3
Design and Characterization of Vertical Mesh Capacitors in Standard CMOS
Abstract K.T. Christensen
Technical University of Denmark, Denmark

9:45

18-4
A JTAG Based AC Leakage Self Test
Abstract T. Rahal-Arabi and G. Taylor
Intel Corporation, USA
back to conference schedule
(Break 10:10-10:30)
Saturday, June 16

Session 19

ADC and Track/Hold [Shunju III]
Chairpersons T. Mori, Fujitsu Labs.
C.-T. Chuang, IBM T.J. Watson Research Center

8:30

19-1
A 1V operational, 20Ms/s and 57dB of S/N, Current-mode CMOS Sample-and-hold IC
Abstract Y. Sugimoto
Chuo University, Japan

8:55

19-2
An 8-bit 30MS/s 18mW ADC with 1.8V single power supply
Abstract T. Sigenobu, M. Ito and T. Miki
Mitsubishi Electric Corporation, Japan

9:20

19-3
A 12-bit Mismatch-Shaped Pipeline A/D Converter
Abstract A. Shabra and H.-S. Lee
Massachusetts Institute of Technology, USA

9:45

19-4
An 8-GHz Bandwidth 1-GS/s GaAs HBT Dual Track-and-Hold
Abstract J.P.A. van der Wagt and M. Teshome
Rockwell Science Center, USA
back to conference schedule
(Break 10:10-10:30)
Saturday, June 16

Session 20

Low Power Design [Shunju I]
Chairpersons K. Seno, Sony
S. Borkar, Intel

10:30

20-1
Comparative Performance, Leakage Power and Switching Power of Circuits in 150nm PD-SOI and Bulk Technologies Including Impact of SOI History Effect
Abstract S. Narendra, J. Tschanz, A. Keshavarzi, S. Borkar and V. De
Intel Corporation, USA

10:55

20-2
A 0.5V Power-Supply Scheme for Low Power LSIs using Multi-Vt SOI CMOS Technology
Abstract T. Fuse, A. Kameyama, M. Ohta and K. Ohuchi
Toshiba Corporation, JAPAN

11:20

20-3
A 0.9-mA Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
Abstract H. Notani, M. Koyama, R. Mano, H. Makino and Y. Matsuda
Mitsubishi Electric Corporation, Japan

11:45

20-4
A 63mW-Standby-Power Microcontroller with On-Chip Hybrid Regulator Scheme
Abstract M. Hiraki, T. Ito, K. Ashiga*, A. Fujiwara, T. Ohashi*, T. Hamano** and T. Noda
Hitachi, Ltd., *Hitachi Device Engineering Co., Ltd. and **Hitachi ULSI Systems Co., Ltd., Japan
back to conference schedule
(Closing 12:10)
Saturday, June 16

Session 21

Embedded RAMs [Shunju II]
Chairpersons N.C.C. Lu, Etron Technology
J. Bowles, AMD

10:30

21-1
Quasi-Worst-Condition Built-In-Self-Test Scheme for 4-Mb Loadless CMOS Four-Transistor SRAM Macro
Abstract K. Takeda, Y. Aimoto, K. Nakamura, S. Masuoka, K. Ishikawa, K. Noda, T. Takeshima and T. Murotani
NEC Corporation, JAPAN

10:55

21-2
A 800MHz Single Cycle Access 32entry Fully Associative TLB With A 240ps Access Match Circuit
Abstract M. Sumita
Matsushita Electric Industrial Co.,Ltd., Japan

11:20

21-3
A Reconfigurable Multilevel Parallel Graphics Cache Memory with 75 GB/s Parallel Cache Replacement Bandwidth
Abstract S.-J. Park, J.-S. Kim, R. Woo, S.-J. Lee, K.-M. Lee, T.-H. Yang*, J.-Y. Jung* and H.-J. Yoo
Korea Advanced Institute of Science and Technology and *HYUNDAI Electronics, Korea

11:45

21-4
A 6.25 ns Random Access 0.25 mm Embedded DRAM
Abstract P. DeMone, M. Dunn, D. Haerle, J.-K. Kim, D. Macdonald, P. Nyasulu, D. Perry, S. Smith, T. Wojcicki and Z. Zhang
MOSAID Technologies Incorporated, Canada
back to conference schedule
(Closing 12:10)
Saturday, June 16

Session 22

RF Front End II [Shunju III]
Chairpersons T. Miki, Mitsubishi Electric
J. Goodman, Chrysalis-ITS

10:30

22-1
A Fully-Integrated 900-MHz CMOS Wireless Receiver with On-Chip RF and IF Filters and 79-dB Image Rejection
Abstract C. Guo, C.-W. Lo, Y.-W. Choi, I. Hsu, T. Kan, D. Leung, A. Chan and H.C. Luong
Hong Kong University of Science and Technology, Hong Kong

10:55

22-2
A Single-Chip 2.4GHz Direct-Conversion CMOS Transceiver with GFSK Modem for Bluetooth Application
Abstract S.-W. Lee, K.-Y. Lee, E. Song, Y.-J. Jung, H. Jeong, J.-M. Kim, H.-J. Lim*, J.-W. Lee*, J. Park*, K. Lee*, S.-I. Chae, D.-K. Jeong and W. Kim
Seoul National University, Korea and *Global Communication Technology, Inc., USA

11:20

22-3
Concurrent Dual-Band CMOS Low Noise Amplifiers and Receiver Architectures
Abstract H. Hashemi and A. Hajimiri
California Institute of Technology, USA

11:45

22-4
Fully Integrated 2.2mW CMOS Front-End for a 900 MHz Zero-IF Wireless Receiver
Abstract S. Mahdavi and A.A. Abidi
University of California, USA
back to conference schedule
(Closing 12:10)


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