2002
SYMPOSIUM ON VLSI TECHNOLOGY
Welcome to the 2002
Symposium on VLSI Technology
On behalf of the organizing
Committees, you are cordially invited to attend
the 2002 Symposium on VLSI Technology to be held
from June 10-13 in Honolulu, Hawaii.
This symposium has established itself as one of
the most prestigious international forums for
presenting the latest research and development in
the area of VLSI technologies and their
applications. This year we have a total of 232
papers submitted from all over the world,
indicating a healthy rebound from last year. From
these excellent works, we selected 84 very high
quality papers, and organized them into 21
sessions. We are also delighted to have two
distinguished Invited Speakers for the Plenary
Session. Prof. D. Antoniadis, MIT, will speak on
"MOSFET Scalability Limits and New Frontier
Devices", and Prof. M. Esashi, Tohoku
University, will address "MEMS Technology
for Optical, Medical, and System-on-a-Chip
Applications".
Four Rump Sessions are planned for the evening of
June 12 as a means to facilitate informal
discussions among researchers. One is a joint
session with the Symposium on VLSI Circuits which
will address "SOC(System-On-a-Chip) vs.
SIP(System-In-a-Package)". The other three
are regular sessions, and will cover specific
technology related topics of timely interest;
| 1) |
Device
limits--Potential of novel structures to
insure continued scaling |
| 2) |
Next generation memory
(NGM) --What memory technology will
displace DRAM and Flash: MRAM, FeRAM, OUM
or New Flash (NROM)? |
| 3) |
Future lithography
roadmap:157 nm or go directly to EUV? |
A one-day Short Course,
scheduled for Monday June 10, will cover
"Key Technology Challenges for Sub-70nm
VLSI". This should be an excellent
opportunity for experienced as well as new
engineers to broaden their technical base.
The symposium registration fee covers all of the
sessions including the Rump Sessions. Coffee
breaks and the dinner are also included.
Registration for the Short Course is extra. The
detailed registration fees and hotel reservation
schedules are included in the Advance Program.
As in past years, we expect a strong
participation from leaders of VLSI industry and
academic researchers. We look forward to an
exciting Symposium in Honolulu. Please join us.
|
Yuan Taur |
Kenji Maeguchi |
| Program Chair |
Program Co-Chair |
CONFERENCE SCHEDULE
Sunday, June 9 |
5:00pm - 8:00pm |
Registration |
| Monday, June 10 |
| 8:00am -
5:00pm |
Registration |
| 8:30am -
5:00pm |
Short Course |
| 7:00pm -
9:00pm |
Technology
Symposium Reception - Lagoon Green |
| Tuesday, June 11 |
| 8:00am -
5:00pm |
Registration |
| 8:30am -
10:15am |
Session 1 |
Welcome
and Plenary Session |
| 10:20am -
12:00pm |
Session 2 |
Highlights
|
| 1:30pm - 3:10pm |
Session 3 |
High-k
Gate Dielectric-I |
| Session 4 |
Interconnects |
| 3:25pm - 5:05pm |
Session 5 |
SOI-I |
| Session 6 |
DRAM
Technology |
| 7:00pm
- 9:00pm |
Technology Symposium Banquet -
Lagoon Green |
| Wednesday, June 12 |
| 8:00am
- 5:00pm |
Registration |
| 8:30am - 10:10am |
Session 7 |
High
Performance Technology |
| Session 8 |
CMOS
Reliability-I |
| 10:25am - 12:05pm |
Session 9 |
High-k
Gate Dielectric-II |
| Session 10 |
Strained
Si Devices |
| 1:30pm - 3:10pm |
Session 11 |
Advanced
CMOS Devices |
| Session 12 |
Advanced
Memory |
| 3:25pm - 5:05pm |
Session 13 |
High
Performance Devices |
| Session 14 |
Process
Technology |
| 8:00pm -
10:00pm |
Rump Sessions |
| Thursday, June 13 |
| 8:00am
- 5:00pm |
Registration |
| 8:30am - 10:10am |
Session 15 |
High-k
Gate Dielectric-III |
| Session 16 |
RF/Analog
Devices |
| 10:25am - 12:05pm |
Session 17 |
SOI-II |
| Session 18 |
DRAM
Cell Technology |
| 1:30pm - 3:10pm |
Session 19 |
High-k
Gate Dielectric-IV |
| Session 20 |
Lithography/Process |
| 3:25pm - 5:05pm |
Session 21 |
Non-Volatile
Memory |
| Session 22 |
CMOS
Reliability-II |
PROGRAM
Session 1 |
Welcome and Plenary Session [Tapa I/II/II] |
| Chairpersons |
Yuan Taur, University
of California, San Diego
Kenji Maeguchi, Toshiba Corporation |
8:20am |
|
Welcome
and Opening Remarks |
| |
Craig Lage, Motorola
Seiichiro Kawamura, Advanced Semi. Research
Center |
8:45am |
1.1 |
MOSFET
Scalability Limits and "New Frontier"
Devices (Invited) |
| |
D. A.
Antoniadis, Massachusetts Institute of
Technology |
9:25am |
1.2 |
MEMS
Technology: Optical Application, Medical
Application and SOC Application (Invited) |
| |
M.
Esashi, Tohoku University |
Session 2 |
Highlights [Tapa I/II/II] |
| Chairpersons |
J. Woo, University
of California, Los Angeles
H. Wakabayashi, NEC Corporation |
10:20am |
2.1 |
Mobility
Enhancement in Strained Si NMOSFETs with HfO2
Gate Dielectrics |
| |
K. Rim, E.P.
Gusev, C. D'Emic, T. Kanarsky*, H. Chen*, J. Chu,
J. Ott, K. Chan, D. Boyd*, V. Mazzeo*, B.H. Lee*,
A Mocuta*, J. Welser*, S.L. Cohen, M. Ieong* a nd
H.-S. Wong, IBM TJ Watson Research Center,
Yorktown Heights, NY and *IBM Microelectronics
Division, Hopewell Junction, NY |
10:45am |
2.2 |
Sub-1m m2
High Density Embedded SRAM Technologies for 100nm
Generation SOC and Beyond |
| Abstract |
K. Tomita,
K. Hashimoto, T . Inbe, T. Oashi, K. Tsukamoto,
Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi,
I. Miyanaga*, M. Nakamura*, T.Kishimoto*, T.
Yamada*, K. Eriguchi*, H. Yuasa*, T. Satake*, A.
Kajiya* and M. Ogura*, Mitsubishi Electric
Corp, Hyogo, Japan and *Matsushita El ectric
Industrial Co., Ltd., Kyoto, Japan |
11:10am |
2.3 |
A
100nm Copper/Low-K Bulk CMOS Technology with
Multi Vt and Multi Gate Oxide Integrated
Transistors for Low Standby Power, High
Performance and RF/Analog System on Chip
Applications |
| Abstract |
G.C.F. Yeap,
J . Chen, P. Grudowski, Y. Jeon, Y. Shiho, W.
Qi*, S. Jallepalli, N. Ramani, K. Hellig*, L.
Vishnubhotla, T. Luo, H. Tseng, Y. Du, S. Lim, P.
Abramowitz, C. Reddy, S. Parihar, R. Singh, M.
Write*, K. Patterson, N. Benavides, D. Bonser*,
T.V. Gompel, J. Connor, J.J. Lee, M. Rendon, D.
Hall, A. Nghiem, R. Stout, K. Weidemann, A.
Duvallet, J. Alvis, D. Dyer, D. Burnett, P.
Ingersoll, K. Wimmer, S. Veeraraghavan, M. Foisy,
M. Hall, J. Pellerin*, D. Wristers*, M. Woo and
C. Lage, Motorola, Inc. and *AMD, Austin, TX |
11:35am |
2.4 |
Advanced
Cu/Low-k (k=2.2) Multilevel Inter-connect for
0.10/0.07m m Generation |
| Abstract |
S.M. Jang,
Y.H. Chen, T.J. Chou, S.N. Lee, C.C. Chen, T.C.
Tseng, B.T. Chen, S.Y. Chang, C.H. Yu and M.S.
Liang, Taiwan Semiconductor Manufacturing
Company, Hsin-Chu, Taiwan, ROC |
Session 3 |
High-k Gate Dielectric-I [Tapa I] |
| Chairpersons |
M. Cao, Pericom
Semiconductor Corporation
T. Hiramoto, University of Tokyo |
1:30pm |
3.1 |
Effects
of High-Temperature Forming Gas Anneal on HfO2
MOSFET Performance |
| Abstract |
K. Onishi,
C.S. Kang, R. Choi, H-J Cho, S. Gopalan, R. Nieh,
S. Krishnan and J.C. Lee, University of
Texas, Austin, TX |
1:55pm |
3.2 |
Metal
Gate MOSFETs with HfO2
Gate Dielectric |
| Abstract |
S.B.
Samavedam, H.H. Tseng , P.J. Tobin, J. Mogab, S.
Dakshina-Murthy*, L.B. La, J. Smith, J.
Schaeffer, M. Zavala, R. Martin, B-Y Nguyen, L.
Hebert, O. Adetutu, V. Dhandapani, T-Y Luo, R.
Garcia, P. Abramowitz, M. Moosa, D.C. Gilmer, C.
Hobbs, W.J. Taylor, J. Grant, R. Hegde, S. B
agchi, E. Luckowski, V. Arunachalam and M. Azrak,
Digital DNA Laboratories, Austin, TX and
*AMD, Austin, TX |
2:20pm |
3.3 |
Specific
Structural Factors Influencing on Reliability of
CVD-HfO2 |
| Abstract |
Y. Harada,
M. Niwa, S. Lee* and D.-L. Kwong*, Matsushita
Electr ic Industrial Co., Ltd., Kyoto, Japan and
*The University of Texas at Austin, Austin, TX |
3:10pm |
3.4 |
Low
Standby Power CMOS with HfO2
Gate Oxide for 100-nm Generation |
| Abstract |
S. Pidin, Y.
Morisaki, Y. Sugita, T. Aoyama, K. Irino, T.
Nakamura and T. Sugii, Fujitsu Laboratories
Ltd., Tokyo, Japan |
Session 4 |
Interconnects [Tapa II] |
| Chairpersons |
R. Havemann,
Novellus Systems
T. Nogami, Sony Corporation |
1:30pm |
4.1 |
Fragile
Porous Low-k/Copper Integration by Using
Electro-Chemical Polishing |
| Abstract |
S.
Takahashi, K. Tai, H. Ohtorii, N. Komai, Y.
Segawa, H. Horikoshi, Z. Yasuda, H. Yamada, M.
Ishihara and T. Nogami, Sony Corporation,
Kanagawa, Japan |
1:55pm |
4.2 |
A
Robust Embedded Ladder-Oxide/Cu Multilevel
Interconnect Technology for 0.13m m CMOS Generation |
| Abstract |
N. Oda, S.
Ito, T. Takewaki, H. Kunishima, N. Hironaga, I.
Honma, H. Namba, S. Yokogawa, T. Goto, T. Usami,
K. Ohto, A. Kubo, H. Aoki, M. Suzuki, Y.
Yamamoto, S. Watanabe, T. Takeda, K. Yamada, M.
Kosaka and T. Horiuchi, NEC Corporation,
Kanagawa, Japan |
2:20pm |
4.3 |
Propagation
Layers for Intra-Chip Wireless Interconnection
Compatible with Packaging and Heat Removal |
| Abstract |
X. Guo, J.
Caserta, R. Li, B. Floyd and K.K. O, University
of Florida, Gainesville, FL |
2:45pm |
4.4 |
Impact
of Joule Heating on Scaling of Deep Sub-Micron
Cu/Low-K Interconnects |
| Abstract |
T-Y Chiang,
B. Shieh and K. Saraswat, Stanford
University, Stanford, CA |
Session 5 |
SOI-I [Tapa I] |
| Chairpersons |
S.
Venkatesan, Motorola
Y. Omura, Kansai University |
3:25pm |
5.1 |
ELFIN
(ELevated
Field INsulator)
and SEP (S/D
Elevated
by Poly-Si
Plugging) Process for Ultra-Thin SOI MOSFETs with
High Performance and High Reliability |
| Abstract |
J.-W. Lee,
H. Takemura*, Y. Saito, R. Koh, S. Yamagami, T.
Mogami, M. Uto, N. Ikezawa and N. Takasu, NEC
Co., Kanagawa, Japan, *New Energy and Industrial
Technology Development Organization (NEDO), Japan |
3:50pm |
5.2 |
Suppression
of Leakage Current in SOI CMOS LSIs by Using
Silicon-Sidewall Body-Contact (SSBC) Technology |
| Abstract |
N. Kotani,
S. Ito, T. Yasui, A. Wada, T. Yamaoka and T.
Hori, Matsushita Electric Industrial Co.,
Ltd., Kyoto, Japan |
4:15pm |
5.3 |
Soft
Error Rate Scaling for Emerging SOI Technology
Options |
| |
P.
Oldiges, K. Bernstein**, D. Heidel*, B.
Klaasen**, E. Cannon**, R. Dennard*, H. Tang*, M.
Ieong and H.S.P Wong*, IBM SRDC, Hopewell
Jucntion, NY and *IBM TJ Watson Research Center,
Yorktown Heights, NY and **IBM Microelectronics,
Essex Junction, VT |
4:40pm |
5.4 |
High
Soft-Error Tolerance Body-Tied SOI Technology
with Partial Trench Isolation (PTI) for Next
Generation Devices |
| Abstract |
Y. Hirano,
T. Iwamatsu, K. Shiga, K. Nii, K. Sonoda, T.
Matsumoto, S. Maeda, Y. Yamaguchi, T. Ipposhi, S.
Maegawa and Y. Inoue, Mitsubishi Electric
Corporation, Hyogo, Japan |
Session 6 |
DRAM Technology [Tapa II] |
| Chairpersons |
C. Dennison,
Ovonyx, Inc.
T. Eimori, Mitsubishi
Electric Corp. |
3:25pm |
6.1 |
A
Highly Manufacturable 110nm DRAM Technology with
8F2
Vertical Transistor Cell for 1Gb and Beyond |
| Abstract |
H. Akatsu,
R. Weis*, K. Cheng, M. Seitz*, M-S Kim*, R.
Ramachandran*, T. Dyer, B. Kim, D-K Kim, R.
Malik*, J. Strane, T. Goebel*, O-J Kwon, C.Y.
Sung, P. Parkinson, K. Wilson, I. McStay*, M.
Chudzik, D. Dobuzins ky, M. Jacunski, C. Ransom,
K. Settlemyer, L. Economikos, A. Simpson*, A.
Knorr*, M. Naeem, G. Stojakovic*, W. Robl*, O.
Gluschenkov, B. Liegl*, C-H Wu, Q. Wu, W-K Li,
C.J. Choi*, N. Arnold*, T. Joseph, K. Varn, M.
Weybright, K. McStay*, W-T Kang*, Y. Li, S.
Bukofsky, R. Jammy, R. Schutz*, A. Gutmann*, W.
Bergner*, R. Divakaruni, D. Back*, E Crabbe, W.
Mueller* and G. Bronner, IBM Microelectronics
and *Infineon Technologies, Hopewell Junction, NY |
3:50pm |
6.2 |
Highly
Manufacturable Sub-100nm DRAM Integrated with
Full Functionality |
| Abstract |
S. Choi,
B.Y. Nam, J.-H. Ku*, D.C. Kim, S.H. Lee, J.J.
Lee, J.W. Lee, J.D. Ryu, S.J. Heo, J.K. Cho, S.P.
Yoon, C.J. Choi, Y.J. Lee, J.H. Chung, B.H. Kim,
M.B. Lee, G.H. Choi, Y.S. Kim, K. Fujihara, U.I.
Chung and J.T. Moon, Samsung Electronics Co.,
Ltd.,Kyoungki-do, Korea |
4:15pm |
6.3 |
A
0.08m m2-Sized
8F2
Stack DRAM Cell for Multi-Gigabit DRAM |
Abstract
|
H. Noh, S.
Jeong, S. Lee, Y. Kim, W. Cho, M. Huh, G. Jeong,
J. Suh, H. Kweon, J. Roh, K. Shin and S. Lee, Hynix
Semiconductor Co., Ltd., Kyungki-Do, Korea |
4:40pm |
6.4 |
Integration
of High Performance Dual Workfunction Logic CMOS
Transistors with a Dense 8F2
Vertical DRAM Cell |
| Abstract |
R.
Rengarajan, R. Malik, H. Yang*, W. Yan*, R.
Ramachandran, B. He*, R. Divakaruni* and Y. Li*, Infineon
Technologies and *IBM Microelectronics, Hopewell
Junction, NY |
Session 7 |
High Performance Technology [Tapa I] |
| Chairpersons |
M-R Lin, AMD
C.H. Diaz, TSMC |
8:30am |
7.1 |
Integration
of High-Performance, Low-Leakage and Mixed Signal
Features into a 100nm CMOS Technology |
| Abstract |
T.
Schafbauer, J. Brighten, Y-C Chen*, L.
Clevenger**, M. Commons, A. Cowley, K. Esmark, A.
Grassman, U. Hodel, H-J Huang**, S-F Huang**, Y.
Huang*, E. Kaltalioglu, G. Knoblinger, M-T Lee*,
A. Leslie, P. Leung*, B. Li**, C. Lin, Y-H Lin*,
W. Nissl, P. Nguyen*, A. Olbrich, P. Riess, N.
Rovedo*, S. Sportouch*, A. Thomas*, D. Vietzke,
M. Wendel, R. Wong*, Q. Ye, K-C Lin**, T. Schiml
and C. Wann*, Infineon Technologies Corp. and
**IBM Microelectron-ics Divisi on and *United
Microelectronics Corp., Hopewell Junction, NY |
8:55am |
7.2 |
UX6-100
nm Generation CMOS Integration Technology with Cu
/Low-K Interconnect |
| Abstract |
K. Fukasaku,
A. Ono, T. Hirai, Y. Yasuda, N. Okada, S. Koyama,
T. Tamura, Y. Yamada, T. Nakata, M. Yamana, N.
Ikezawa, T. Matsuda, K. Arita, H. Nambu, A.
Nishizawa, K. Nakabeppu and N. Nakamura, NEC
Corporation, Kanagawa, Japan |
9:20am |
7.3 |
A
100 nm CMOS Technology with
"Sidewall-Notched" 40 nm Transistors
and SiC-Capped Cu/VLK Interconnects for High
Performance Microprocessor Applications |
| Abstract |
S. Nakai, Y.
Takao, S. Otsuka, K. Sugiyama, H. Ohta, A.
Yamanoue, Y. Iriyama, R. Nanjyo, S. Sekino, H.
Nagai, K. Naitoh, R. Nakamura, Y. Sambonsugi, Y.
Tagawa, N. Horiguchi, T. Yamamoto, M. Kojima, S.
Satoh, S. Sugatani, T. Sugii, M. Kase*, K.
Suzuki**, M. Nakaishi**, M. Miyajima*, T. Ohba*,
I. Hanyu* and K. Yanai, Fujitsu Laboratories,
Tokyo, Japan and *Fujitsu Limited, Tokyo, Japan
and **Fujitsu Limited., Mie, Japan |
9:45am |
7.4 |
Extended
0.13m m CMOS Technology for the Ultra
High-Speed and MS/RF Application Segments |
| Abstract |
C.S. Chang,
C.P. Chao, Y.K. Leung, C.H. Lin, H.-M. Hsu, Y.P.
Wang, S.Y. Chang, T.H. Chiu, J.S. Shyu, C.C. Wu,
C.H. Wang, R.Y. Chang, C.W. Chen, C.F. Huang,
C.H. Chen, S.H. Chen, T.H. Yeh, J.Y. Cheng, J.J.
Liaw, Y.L. Chu, T.C. Ong, M.C. Yu, C.H. Yu, H.J.
Lin, H.J. Tao, M.S. Liang, Y.C. See, C.H. Diaz
and Y.C. Sun, TSMC, Hsin-Chu, Taiwan, ROC |
Session 8 |
CMOS Reliability-I [Tapa II] |
| Chairpersons |
S. Broydo, Applied
Materials
H. Oyamatsu, Toshiba COrporation |
8:30am |
8.1 |
Avoiding
Plasma Induced Damage to Gate Oxide with
Conductive Top Film (CTF) on PECVD Contact Etch
Stop Layer |
| Abstract |
S.-C. Song,
S. Filipiak, A. Perera, M. Turner*, F. Huang,
S.G.H. Anderson, L. Kang, B. Min, D. Menke, S.
Tukunang and S. Venkatesan, Motorola, Austin,
TX and *Advanced Micro Devices, Austin, TX |
8:55am |
8.2 |
A
Novel and Direct Determination of the Interface
Traps in Sub-100nm CMOS Devices with Direct
Tunneling Regime (12~16A) Gate Oxide |
| Abstract |
S.S. Chung,
S.-J. Chen, C.-K. Yang*, S.-M. Cheng*, S.-H.
Lin*, Y.-C. Sheng*, H.-S. Lin*, K.-T. Hung*,
D.-Y. Wu*, T.-R. Yew*, S.-C. Chien*, F.-T. Liou*
and F. Wen*, National Chiao Tung University,
Taiwan and *UMC, Hsinchu, Taiwan |
9:20am |
8.3 |
Strong
Correlation Between Dielectric Reliability and
Charge Trapping in SiO2/Al2O3
Gate Stacks with TiN Electrodes |
| Abstract |
A. Kerber,
E. Cartier*, R. Degraeve**, L. Pantisano**, P.
Roussel** and G. Groeseneken**, Infineon
Technologies AG and *IBM Research Division and
**IMEC, International Sematech, Institute fur
Halbleiter-technik TU-Darmstadt, Leuven, Belgium |
9:45am |
8.4 |
Reliability
Projection and Polarity Dependence of TDDB for
Ultra Thin CVD HfO2 Gate
Dielectrics |
| Abstract |
S.J. Lee,
S.J. Rhee, R. Clark* and D.L. Kwong, University
of Texas, Austin, TX and *Schumacher, Carlsbad,
CA |
Session 9 |
High-k Gate Dielectric-II [Tapa I] |
| Chairpersons |
J. Watt,
Cypress Semiconductor
M. Niwa, Matsushita
Electric Industrial Co., Ltd. |
10:25am |
9.1 |
Self-Aligned
Ultra Thin HfO2
CMOS Transistors with High Quality CVD TaN Gate
Electrode |
| Abstract |
C.H. Lee,
J.J. Lee, W.P. Bai, S.H. Bae, J.H. Sim, X. Lei*,
R.D. Clark*, Y. Harada**, M. Niwa** and D.L.
Kwong, University of Texas, Austin, TX and
*Schumacher, Carlsbad, CA and **Matsushita,
Kyoto, Japan |
10:50am |
9.2 |
Poly-Si
Gate CMOSFETs with HfO2-Al2O3
Laminate Gate Dielectric for Low Power
Applications |
| Abstract |
J.-H. Lee,
Y.-S. Kim, H.-S. Jung, J.-H. Lee, N.-I. Lee,
H.-K. Kang, J.-H. Ku, H.S. Kang, Y.-K. Kim, K.-H.
Cho and K.-P. Suh, Samsung Electronics Co.,
Ltd., Kyunggi-Do, Korea |
11:15am |
9.3 |
Improved
Performance of Ultra-Thin HfO2
CMOSFETs Using Poly-SiGe Gate |
| Abstract |
Q. Lu, H.
Takeuchi, X. Meng, T-J King, C. Hu, K. Onishi*,
H-J Cho* and J. Lee*, University of
California, Berkeley, CA and *University of
Texas, Austin, TX |
11:40am |
9.4 |
Improved
Film Growth and Flatband Voltage Control of ALD
HfO2
and Hf-Al-O with n+
Poly-Si Gates Using Chemical Oxides and Optimized
Post-Annealing |
| Abstract |
G. Wilk, M.
Green, M-Y Ho*, B. Busch, T. Sorsch, F. Klemens,
B. Brijs**, R. van Dover, A. Kornblit, T.
Gustafsson^, E. Garfunkel^, S. Hillenius, D.
Monroe, P. Kalavade and J. Hergenrother, Agere
Systems, Murray Hill, NJ and *National Univ. of
Singapore, Singapore and **IMEC, Heverlee,
Belgium and ^Rutgers University, Piscataway, NY |
Session 10 |
Strained Si Devices [Tapa II] |
| Chairpersons |
J. Lee, University
of Texas
T. Tsuchiya, Shimane
University |
10:25am |
10.1 |
Fabrication
of a Novel Strained SiGe:C-Channel Planar 55nm
nMOSFET for High-Performance CMOS |
| Abstract |
T. Ernst,
J-M Hartmann, V. Loup, F. Ducroquet*, P.
Dollfus**, G. Guegan, D. Lafond, P. Holliger, B.
Prévitali, A. Toffoli and S. Deleonibus, CEA-LETI,
Grenoble Cedex, France and *LPM, INSA-Lyon,
Villeurbanne Cedex, France and **IEF, Université
Paris-Sud, Orsay, France |
10:5am |
10.2 |
<100>
Channel Strained-SiGe p-MOSFET with Enhanced Hole
Mobility and Lower Parasitic Resistance |
| Abstract |
M. Shima, T.
Ueno, T. Kumise, H. Shido, Y. Sakuma and S.
Nakamura, Fujitsu Laboratories Ltd., Atsugi,
Japan |
11:15am |
10.3 |
High
Performance Strained Si-on-Insulator MOSFETs by
Novel Fabrication Processes Utilizing
Ge-Condensation Technique |
| Abstract |
T. Tezuka,
N. Sugiyama, T. Mizuno and S. Takagi, Association
of Super-Advanced Electronics Technology (ASET),
Kawasaki, Japan |
11:40am |
10.4 |
Characteristics
and Device Design of Sub-100nm Strained SiN- and
PMOSFETs |
| |
K. Rim, J.
Chu, H. Chen*, K.A. Jenkins, T. Kanarsky*, K.
Lee, A. Mocuta*, H. Zhu*, R. Roy, J. Newbury, J.
Ott, K. Petrarca*, P. Mooney, D. Lacey, S.
Koester, K. Chan, D. Boyd*, M. Ieong* and H-S
Wong, IBM TJ Watson Research Center, Yorktown
Heights, NY and *IBM Microelectronics, Hopewell
Junction, NY |
Session 11 |
Advanced CMOS Devices [Tapa I] |
| Chairpersons |
Y.
Ponomarev, Philips Research Leuven
S. Chung, Nat’l
Chiao Tung University |
1:30pm |
11.1 |
Supply
Voltage Strategies for Minimizing the Power of
CMOS Processors |
| Abstract |
J. Cai, Y.
Taur, S-F Huang, D. Frank, S. Kosonocky and R.H.
Dennard, IBM TJ Watson Research Center,
Yorktown Heights, NY |
1:55pm |
11.2 |
35nm
CMOS FinFETs |
| Abstract |
F.-L. Yang,
H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang,
C.-J. Chen, H.-H. Tao, Y.-K. Choi, M.-S. Liang
and C. Hu, Taiwan Semiconductor Manufacturing
Company, Ltd., Hsin-Chu, Taiwan, ROC |
2:20pm |
11.3 |
High
Performance CMOS Operation of Strained-SOI
MOSFETs using Thin Film SiGe-on-Insulator
Substrate |
| Abstract |
T. Mizuno,
N. Sugiyama, T. Tezuka, T. Numata and S. Takagi, Association
of Super-Advanced Electronics Technology (ASET),
Kawasaki, Japan |
2:45pm |
11.4 |
50nm-Gate
All Around (GAA) - Silicon On Nothing (SON) -
Devices: A Simple Way to Co-Integration of GAA
Transistors within Bulk MOSFET Process |
| Abstract |
S.
Monfray*^***, T. Skotnicki*, Y. Morand*, S.
Descombes*, P. Coronel*, P. Mazoyer*, S.
Harrison***, P. Ribot*, A. Talbot*, D. Dutartre*,
M. Haond*, R. Palla*, Y. Le Friec*, F. Leverd*,
M-E Nier*, C. Vizioz** and D. Louis**, *STMicroelectronics,
Crolles, France and ^France Telecom R&D,
Meylan, France and **CEA-LETI, Grenoble, France
and ***Université de Provence, Marseille, France |
Session 12 |
Advanced Memory [Tapa II] |
| Chairpersons |
S. Crowder, IBM
Microelectronics
T. Nakamura, Rohm Co.,
Ltd. |
1:30pm |
12.1 |
An
Embedded DRAM Technology on SOI/Bulk Hybrid
Substrate Formed with SEG Process for High-End
SOC Application |
| Abstract |
T. Yamada,
K. Takahashi*, H. Oyamatsu, H. Nagano, T. Sato,
I. Mizushima, S. Nitta, T. Hojo, K. Kokubun, K.
Yasumoto, Y. Matsubara, T. Yoshida, S. Yamada, Y.
Tsunashima, Y. Saito, S. Nadahara, Y. Katsumata,
M. Yoshimi and H. Ishiuchi, Toshiba
Corporation, Kanagawa, Japan and * Toshiba
Microelectronics Corp., Kanagawa, Japan |
1:55pm |
12.2 |
Practical
Next Generation Solution for Stand-Alone and
Embedded DRAM Capacitor |
| Abstract |
J.-H. Lee,
J.-H. Lee, Y.-S. Kim, H.-S. Jung, N.-I. Lee,
H.-K. Kang and K.-P. Suh, Samsung Electronics
Co., Ltd., Kyunggi-Do, Korea (ROK) |
2:20pm |
12.3 |
A
Ferroelectric Analog Associative Memory
Technology Employing Hetero-Gate
Floating-Gate-MOS Structure |
| Abstract |
D.
Kobayashi, T. Shibata, Y. Fujimori*, T. Nakamura*
and H. Takasu*, The University of Tokyo,
Tokyo, Japan, *ROHM Co., Ltd. |
2:45pm |
12.4 |
Highly
Manufacturable 32Mb ULP-SRAM Technology by Using
Dual Gate Process for 1.5V Vcc Operation |
| Abstract |
D.H. Kim,
S.J. Kim, B.J. Hwang, S.H. Seo, J.H. Choi, H.S.
Lee, W.S. Yang, M.S. Kim, K.H. Kwak, J.Y. Lee,
J.Y. Joo, J.H. Kim, K. Koh, S.H. Park and J.I.
Hong, Samsung Electronics Co., Ltd.,
Kyungki-Do, Korea |
Session 13 |
High Performance Devices [Tapa I] |
| Chairpersons |
P. Zeitzoff,
International Sematech
T. Dan, Sanyo Electric
Co., Ltd. |
3:25pm |
13.1 |
0.65
V Device Design with High-Performance and
High-Density 100nm CMOS Technology for Low
Operation Power Application |
| Abstract |
Y. Takao, S.
Nakai, Y. Tagawa, S. Otsuka, Y. Sambonsugi, K.
Sugiyama, H. Oota, Y. Iriyama, R. Nanjyo, H.
Nagai, K. Naitoh, R. Nakamura, S. Sekino, A.
Yamanoue, N. Horiguchi, T. Yamamoto, M. Kojima,
S. Satoh, T. Sugii, M. Kase*, K. Suzuki**, M.
Nakaishi**, M. Miyajima*, T. Ohba*, I. Hanyu* and
S. Sugatani, Fujitsu Laboratories, Ltd.,
Tokyo, Japan and *Fujitsu Limited, Tokyo, Japan
and **Fujitsu Limited, Mie, Japan |
3:50pm |
13.2 |
60nm
Gate Length Dual-Vt CMOS for High Performance
Applications |
| Abstract |
M. Mehrotra,
J. Wu, A. Jain, T. Laaksonen, K. Kim, W. Bather,
R. Koshy, J. Chen, J. Jacobs, V. Ukraintsev, L.
Olsen, J. DeLoach, J. Mehigan, R. Agarwal, S.
Walsh, D. Sekel, L. Tsung, M. Vaidyanathan, B.
Trentman, K. Liu, S. Aur, R. Khamankar, P.
Nicollian, Q. Jiang, Y. Xu, B. Campbell, P.
Tiner, R. Wise, D. Scott and M. Rodder, Texas
Instruments, Dallas, TX |
4:15pm |
13.3 |
A
New Double-Layered Structure for
Mass-Production-Worthy CMOSFETs with Poly-SiGe
Gate |
| Abstract |
H.S. Rhee,
J.I. Lee, S.S. Kim, G.J. Bae, N.I. Lee, D.H. Kim,
J.I. Hong, H.-K. Kang and K.P. Suh, Samsung
Electronics Co., Ltd., Kyunggi-Do, Korea |
4:40pm |
13.4 |
Novel
Polycrystalline Gate Engineering for High
Performance Sub-100 nm CMOS Devices |
| Abstract |
K. Uejima,
T. Yamamoto and T. Mogami, NEC Corporation,
Kanagawa, Japan |
Session 14 |
Process Technology [Tapa II] |
| Chairpersons |
S. Yeh, LSI
Logic Corp.
K. Shibahara, Hiroshima
University |
3:25pm |
14.1 |
Void
Free and Low Stress Shallow Trench Isolation
Technology Using P-SOG for Sub 0.1m m Device |
| Abstract |
J.-H. Heo,
S.-J. Hong, D.-H. Ahn, H.-D. Cho, M.-H. Park, K.
Fujihara, U.-I. Chung, Y.-C. Oh and J.-T. Moon, Samsung
Electronics Co., Ltd., Kyungki-Do, Korea |
3:50pm |
14.2 |
Gate
Postdoping to Decouple Implant/Anneal for Gate,
Source/Drain, and Extension: Maximizing
Polysilicon Gate Activation for 0.1m m CMOS Technologies |
| Abstract |
H. Park, D.
Schepis, A.C. Mocuta, M. Khare, Y.Li, B. Doris,
S. Shukla, T. Hughes, O. Dokumaci, S. Narasimha,
S. Fung, J. Snare, B.H. Lee, J. Li, P. Ronsheim,
A. Domenicucci, P. Varekamp, A. Ajmera, J.
Sleight, P. O'Neil, E. Maciejewski and C.
Lavoie*, IBM Microelectronics SRDC, Hopewell
Junction, NY and *IBM TJ Watson Research Center,
Yorktown Heights, NY |
4:15pm |
14.3 |
A
Novel Bi-layer Cobalt Silicide Process with
Nitrogen Implantation for sub-50nm CMOS and
Beyond |
| Abstract |
K. Itonaga,
K. Eriguchi, I. Miyanaga, A. Kajiya, M. Ogura, T.
Tsutsumi*, H. Sayama*, H. Oda*, T. Eimori* and H.
Morimoto, Matsushita Electric Industrial Co.,
Ltd. and *Mitsubishi Electric Corporation |
4:40pm |
14.4 |
Drive
Current Enhancement by Ideal Junction Profile
Using Laser Thermal Process |
| Abstract |
T. Yamamoto,
K. Goto, Y. Tada, Y. Kikuchi, T. Kubo*, Y.
Wang**, S. Talwar**, M. Kase* and T. Sugii, Fujitsu
Laboratories Ltd., Tokyo, Japan and *Fujitsu
Ltd., Tokyo, Japan and **Verdant Technologies,
San Jose, CA |
Wednesday,
June 12
8:00pm - 10:00pm |
Rump Sessions [Tapa III,
Honolulu I, II, III] |
| Organizers |
C.
Dennison, Ovonyx
T. Eimori, Mitsubishi
Electric |
| Joint
Rump Session |
SOC
(System-On-a-Chip) vs. SIP (System-In-a-Package) |
| Moderator |
J.
Goodman, Lumic Electronics
|
| Organizers |
Technology
D. Buss, Texas Instruments
T. Suga, University of Tokyo |
Circuits
J. Goodman, Lumic Electronics
T. Sakurai, University of Tokyo |
In
the Internet Age, growth areas for solid-state
circuits are in personal internet products (e.g.,
cell phones, PDAs, Internet audio players, and
portable video players/recorders) and the
networks used to connect these products (e.g.,
short distance wireless, DSL modems, cable
modems, and eventually fiber to the home and
office). These applications all require
integration to achieve cost reduction. The panel
will explore the question of whether cost
reduction will result from SoC integration or SiP
integration, or through a new kind of integration
called heterogeneous integration.
|
| |
| R-2 |
Do We Really Need a
New MOSFET Structure? |
| Moderators |
D.
Frank, IBM
M. Yoshimi, Toshiba
|
Novel
devices (e.g., strained-Si MOSFET, double gate
structures, FinFET, vertical MOSFET, etc.) have
various attractive features that represent
improvements over conventional planar structures,
such as high drive current, reduced short channel
effect, fluctuation-resistant channel structure,
and lithography-independent gate formation. On
the other hand, recent experimental data show
that conventional planar-type MOSFETs seem to be
extendable down to less than 20nm gate length,
which is not far from the currently-predicted
theoretical limit of high-performance scaling.
Do we really need any of these novel MOSFET
structures? If yes, why?, when?, and what
structure? What advantages do they offer in
different application scenarios? If no, how can
we overcome the numerous issues in scaling bulk
Si MOSFETs to the very end?
|
| |
| R-3 |
Next Generation
Memory - What Memory Technology will Displace
Flash and DRAM? |
| Moderators |
R. Bez, STMicroelectronics
Y. Terada, Mitsubishi
Electric
|
One
of the most significant phenomena of the past
decade in the field of semiconductor memories has
been the explosive growth of the Flash memory
market, driven by cellular phones and other types
of electronic portable equipment (palm top,
mobile PC, mp3 audio player, digital camera and
so on).
Portable systems are demanding non-volatile
memory at increasing density with very high
writing throughput for data storage application
and high performance (non-volatile) memory with
fast random access for execution in place.
From this point of view, the current
semiconductor memories have limitations: Flash
has limited endurance and is slow in programming.
High voltages required for write operation make
the scaling of Flash very difficult. DRAM is
volatile and requires complicated memory cell
structure.
Hence the search for future memory technologies
has started with the dream of finding the
Universal Memory that will be able to combine
fast read, fast write, non-volatility, low power,
unlimited endurance and obviously at a cost
comparable with the Flash or DRAM.
Industrial interest is growing rapidly for new
technologies that exploit new materials and
physical storage concepts like polarization state
in ferroelectrics (FeRAM and Polymeric FeRAM),
crystallographic state in chalcogenide phase
change (OUM or PCM), electron spin in magnetic
(MRAM) and discrete traps in "new
Flash".
In this rump session the emerging non-volatile
memory technologies will be discussed. MRAM,
FeRAM or PFRAM, OUM and new Flash will be
presented and compared in terms of the main
parameters such as bit size, cost, scalability,
endurance, reliability, write time and energy,
maturity and potential application.
|
| |
| R-4 |
Is 157nm Optical
Lithography Worthwhile, or Should We Go Directly
to EUV? |
| Moderators |
P. Silverman, Intel
W. Wakamiya,
Selete
|
Exposure
tool suppliers are actively developing both 157nm
and EUV scanners as the tools for advanced
optical lithography. Although 157nm scanners are
targeted at the 65nm node, the first tools will
not be available until late 2004/early
2005. This is too late to intersect the
65nm node at leading edge companies.
Therefore it is likely that 157nm will be pushed
out to the 45nm node, in competition with
EUVL. In addition, there are a number of
significant technical issues which could further
delay 157nm. Redesign to accommodate a
"no pellicle" solution could take 6-9
months; CaF2 yields could constrain
157nm capacity; and tool costs could be very
high, especially if >0.85NA tools are
needed. The total market size for 157nm
scanners is probably smaller that the market for
DUV and 193nm scanners. This makes 157nm
investments risky for suppliers. With these
factors in mind, skipping 157nm and going
directly to EUV looks attractive.
On-the-other-hand, EUV has significant
risks. Defect levels on EUV mask blanks are
still too high to allow economical mask
production. Without significant
increases in source power, EUV scanner run rates
will be too low for high volume
manufacturing. Furthermore, EUV is a
significant jump from the learning base of
traditional optical lithography. Big
changes always open the door for big risks and
big delays. Although, other lithography
technologies such as EPL, MEBW are being
developed. We would like to focus the discussion
on optical lithography.
So should the industry skip 157nm and go directly
to EUV or is this too large a risk? It will
be interesting to hear the thinking or our panel
of experts from suppliers and the semiconductor
industry.
|
Session 15 |
High-k Gate Dielectric-III [Tapa I] |
| Chairpersons |
S.
Deleonibus, IMEC
S. Onishi, Sharp Corp. |
8:30am |
15.1 |
Improved
Thermal Stability and Device Performance of
Ultra-Thin (EOT<10Å) Gate Dielectric MOSFETs
by Using Hafnium Oxynitride (HfOxNy) |
| Abstract |
C.S. Kang,
H.-J. Cho, K. Onishi, R. Choi, R. Nieh, S.
Goplan, S. Krishnan and J.C. Lee, University
of Texas at Austin, Austin, TX |
8:55am |
15.2 |
Advanced
CMOS Transistors with a Novel HfSiON Gate
Dielectric |
| Abstract |
A.
Rotondaro, M. Visokay, J. Chambers, A. Shanware,
R. Khamankar, H. Bu, R. Laaksonen, L. Tsung, M.
Douglas, R. Kuan, M. Bevan, T. Grider, J.
McPherson and L. Colombo, Texas Instruments,
Inc., Dallas, TX |
9:20am |
15.3 |
Femto-Second
CMOS Technology with High-k Offset Spacer and SiN
Gate Dielectric with Oxygen-Enriched Interface |
| Abstract |
R. Tsuchiya,
K. Ohnishi, M. Horiuchi, S. Tsujikawa, Y.
Shimamoto, N. Inada, J. Yugami, F. Ootsuka and T.
Onai, Hitachi, Ltd., Tokyo, Japan |
9:45am |
15.4 |
Hot-Carrier
Charge Trapping and Reliability in High-K
Dielectrics |
| Abstract |
A. Kumar,
T.H. Ning, M.V. Fischetti and E. Gusev, IBM
TJ Watson Research Center, Yorktown Heights, NY |
Session 16 |
RF/Analog Devices [Honolulu Suites] |
| Chairpersons |
B. Zhao, Conexant
Systems, Inc.
Y. Takao, Fujitsu Laboratories, Ltd. |
8:30am |
16.1 |
110
GHz Cutoff Frequency of Ultra-Thin Gate Oxide
p-MOSFETs on (110) Surface-Oriented Si Substrate |
| Abstract |
H. Sasaki
Momose, T. Ohguro, K. Kojima, S. Nakamura and Y.
Toyoshima, Toshiba Corporation, Yokohama,
Japan |
8:55am |
16.2 |
Improvement
of High Resistivity Substrate for Future Mixed
Analog-Digital Applications |
| |
T. Ohguro,
K. Kojima, H.S. Momose, S. Nitta, T. Fukuda, T.
Enda and Y. Toyoshima, Toshiba Corp.,
Yokohama, Japan |
9:20am |
16.3 |
A
Porous Si Based Novel Isolation Technology for
Mixed-Signal Integrated Circuits |
| Abstract |
H-S Kim, K.
Chong, Y-H Xie, M. Devincentis, T. Itoh, A.J.
Becker* and K.A. Jenkins**, University of
California, Los Angeles, CA and *Agere Systems,
Murray Hill, NJ and **IBM TJ Watson Research
Center, Yorktown Heights, NY |
9:45am |
16.4 |
A
1.4dB Insertion-Loss, 5GHz Transmit/Receive
Switch Utilizing Novel Depletion-Layer-Extended
Transistors
(DETs) in 0.18m m CMOS Process |
| Abstract |
T. Ohnakado,
A. Furukawa, M. Ono*, E. Taniguchi*, S. Yamakawa,
K. Nishikawa, T. Murakami, Y. Hashizume, K.
Sugahara and T. Oomori, Mitsubishi Electric
Corporation, Hyogo, Japan and *Kanagawa, Japan |
Session 17 |
SOI-II [Tapa I] |
| Chairpersons |
K. DeMeyer, IMEC
T. Hiramoto, University
of Tokyo |
10:25am |
17.1 |
A
45nm Gate Length High Performance SOI Transistor
for 100nm CMOS Technology Applications |
| Abstract |
M. Celik, S.
Krishnan*, M. Fuselier, A. Wei, D. Wu, B. En*, N.
Cave, P. Abramowitz, B. Min, M. Pelella*, P.
Yeh*, G. Burbach, B. Taylor, Y. Jeon, W-J Qi, R.
Li, J. Conner, G. Yeap, M. Woo, M. Mendicino, O.
Karlsson* and D. Wristers, AMD and Motorola
Technology Development Alliance, Austin, TX and
*AMD Logic Technology Development, Sunnyvale, CA |
10:50am |
17.2 |
High
Performance 60nm CMOS Technology Enhanced with
BST (Body-Slightly-Tied) Structure SOI and
Cu/Low-k (k=2.9) Interconnect for Microprocessors |
| Abstract |
T. Kudo, S.
Miyake, T. Syo, S. Maruyama, Y. Yama, T. Katou,
T. Tanaka, T. Matuda, M. Ikeda, K. Imai and H.
Ooka, NEC Corporation, Kanagawa, Japan |
11:15am |
17.3 |
70nm
Fully-Depleted SOI CMOS Using a New Fabrication
Scheme: The Spacer/Replacer Scheme |
| Abstract |
H. van Meer
and K. De Meyer, IMEC Leuven, Belgium and
K.U. Leuven, Leuven, Belgium |
11:40am |
17.4 |
Fully-Depleted-Collector
Polysilicon-Emitter SiGe-Base Vertical Bipolar
Transistor on SOI |
| Abstract |
J. Cai, A.
Ajmera*, C. Ouyang, P. Oldiges*, M. Steigerwalt*,
K. Stein*, K. Jenkins, G. Shahidi* and T. Ning, IBM
Research Center, Yorktown Heights, NY and *IBM
Microelectronics, Hopewell Junction, NY |
Session 18 |
DRAM Cell Technology [Honolulu Suites] |
| Chairpersons |
J. Woo, University
of California, Los Angeles
D-H Lee, Hynix
Semiconductor Inc., Ltd. |
10:25am |
18.1 |
Novel
DRAM Cell Transistor with Asymmetric Source and
Drain Junction Profiles Improving Data Retention
Characteristics |
| Abstract |
S.J. Ahn,
G.T. Jung, C.H. Cho, S.H. Shin, J.Y. Lee, J.G.
Lee, H.S. Jeong and K. Kim, Samsung
Electronics Co., Ltd., Kyunggi-Do, Korea |
10:50am |
18.2 |
Integration
of Capacitor for Sub-100-nm DRAM Trench
Technology |
| Abstract |
J. Lützen,
A. Birner, M. Goldbach, M. Gutsche, T. Hecht, S.
Jakschik, A. Orth, A. Sänger, U. Schröder, H.
Seidl, B. Sell and D. Schumann, Infineon
Technologies, Dresden, Germany |
11:15am |
18.3 |
Vertical
Pass Transistor Design for Sub-100nm DRAM
Technologies |
| |
K. McStay,
D. Chidambarrao*, J. Mandelman*, J. Beintner, H.
Tews, M. Weybright*, G. Wang*, Y. Li*, K.
Hummler, R. Divakaruni*, W. Bergner, E. Crabbé*,
G. Bronner* and W. Mueller, Infineon
Technologies and *IBM Microelectronics, Hopewell
Junction, NY |
11:40am |
18.4 |
A
Novel Bit Line - SToFM (Spacerless
Top-Flat
Mask) -
Technology for 90nm DRAM Generation and Beyond |
| Abstract |
B.J. Park,
Y.S. Hwang, Y.N. Hwang, J.W. Lee, K.H. Lee, K.T.
Jeong, H.S. Jeong, Y.J. Park and K. Kim,
Samsung Electronics Co., Kyunggi-Do, Korea |
Session 19 |
High-k Gate Dielectric-IV [Tapa I] |
| Chairpersons |
C.S. Pai, Agere
Systems
J. Ida, Oki Electric
Industry Co., Ltd. |
1:30pm |
19.1 |
Comparison
Between Ultra-Thin ZrO2
and ZrOxNy
Gate Dielectrics in TaN or
Poly-Gated NMOSCAP and NMOSFET Devices |
| Abstract |
R. Nieh, S.
Krishnan, H-J Cho, C.S. Kang, S. Gopalan, K.
Onishi, R. Choi and J.C. Lee, University of
Texas, Austin, TX |
1:55pm |
19.2 |
The
Mechanism of Mobility Degradation in MISFETs with
Al2O3
Gate Dielectric |
| Abstract |
K. Torii, Y.
Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y.
Manabe*, M. Caymax* and J.W. Maes**, Hitachi
Ltd., Tokyo, Japan and *IMEC, Leuven, Belgium and
**ASM International NV, Bilthoven, The
Netherlands |
2:20pm |
19.3 |
Effect
of In-Situ Nitrogen Doping into MOCVD-Grown Al2O3
to Improve Electrical Characteristics of MOSFETs
with Polysilicon Gate |
| Abstract |
Y. Tanida,
Y. Tamura, S. Miyagaki, M. Yamaguchi, C. Yoshida,
Y. Sugiyama and H. Tanaka, Fujitsu
Laboratories Ltd., Atsugi, Japan |
2:45pm |
19.4 |
Thermal
Stability and Scalability of Zr-Aluminate-Based
High-K Gate Stacks |
| |
P.J. Chen 1,3,
E. Cartier 2,3, R.J. Carter*, T.
Kauerauf*, C. Zhao*, J. Petry*, V. Cosnier
3,5, Z. Xu*, A. Kerber 3,6, W.
Tsai 3,7, E. Young3,8, S.
Kubicek*, M. Caymax*, W. Vandervorst*, S.
DeGendt*, M. Heyns*, M. Copel2, W.
Besling8, P. Bajolet9 and
J. Maes9, 1Texas
Instruments, Inc. and 2IBM
Research Division, 3International
Sematech, *IMEC, 5ST-Microelect-ronics,
6Infineon Techn AG, 7Intel,
Inc., 8Philips, 9ASM
International NV, Leuven, Belgium |
Session 20 |
Lithography/Process [Honolulu Suites] |
| Chairpersons |
D. Shum, Infineon
Technologies
H. Wakabayashi, NEC
Corp. |
1:30pm |
20.1 |
Lithography
Solution for 65-nm Node System LSIs |
| Abstract |
T. Matsuo,
M. Endo, S. Kishimura, A. Misaka and M. Sasago, Matsushita
Electric Industrial Co., Ltd., Kyoto, Japan |
1:55pm |
20.2 |
Novel
Resist Pattern Transfer Process for 70nm
Technology Node Using 157-nm Lithography |
| Abstract |
S. Miyoshi,
T. Furukawa, H. Watanabe, S. Irie and T. Itani, Semiconductor
Leading Edge Technologies, Inc. (Selete),
Yokohama, Japan |
2:20pm |
20.3 |
Super-Resolution
Enhancement Method With Phase-Shifting Mask
Available for Random Patterns |
| Abstract |
A. Misaka,
T. Matsuo and M. Sasago, Matsushita Electric
Industrial Co., Ltd., Kyoto, Japan |
2:45pm |
20.4 |
An
Ultra-Thin Silicon Nitride Gate Dielectric with
Oxygen-Enriched Interface (OI-SiN) for CMOS with
EOT of 0.9 nm and Beyond |
| Abstract |
S.
Tsujikawa, T. Mine, Y. Shimamoto, O. Tonomura, R.
Tsuchiya, K. Ohnishi, H. Hamamura, K. Torii, T.
Onai and J. Yugami, Hitachi, Ltd., Tokyo,
Japan |
Session 21 |
Non-Volatile Memory [Tapa I] |
| Chairpersons |
R. Bez, STMicroelectronics
S. Chung, Nat’l Chiao Tung University |
3:25pm |
21.1 |
A
Novel 2-Bit/Cell MONOS Memory Device with a
Wrapped-Control-Gate Structure that Applies
Source-Side Hot-Electron Injection |
| Abstract |
H. Tomiye,
T. Terano, K. Nomoto and T. Kobayashi, Sony
Corporation Semiconductor Network Company,
Kanagawa, Japan |
3:50pm |
21.2 |
Multi-Level
Vertical Channel SONOS Nonvolatile Memory on SOI |
| Abstract |
Y.K. Lee,
S.K. Sung, J.S. Sim, S.H. Lee, J.D. Lee, B.G.
Park, D.H. Lee* and Y.W. Kim*, Seoul National
University, Seoul, Korea and *Samsung Electronics
Industries Co. Ltd., Kyunggi-Do, Korea |
4:15pm |
21.3 |
Novel
Integration Technologies for Highly
Manufacturable 32Mb FRAM |
| Abstract |
H.H. Kim,
Y.J. Song, S.Y. Lee, H.J. Joo, N.W. Jang, D.J.
Jung, Y.S. Park, S.O. Park, K.M. Lee, S.H. Joo,
S.W. Lee, S.D. Nam and K. Kim, Samsung
Electronics Co. Ltd., Kyungki-Do, Korea |
4:40pm |
21.4 |
High-Performance
MRAM Technology with an Improved Magnetic Tunnel
Junction Material |
| Abstract |
M.
Motoyoshi, K. Moriyama*, H. Mori*, C. Fukumoto*,
H. Itoh*, H. Kano, K. Bessho and H. Narisawa, Sony
Corporation, Kanagawa, Japan and *Sony
Semicon-ductor Kyushu, Kyushu, Japan |
Session 22 |
CMOS Reliability-II [Honolulu Suites] |
| Chairpersons |
J. Wu, Texas
Istruments
M. Niwa, Matsushita
Electric Ind. Co., Ltd. |
3:25pm |
22.1 |
A
Strategy Using a Copper/Low-k BEOL Process to
Prevent Negative-Bias Temperature Instability
(NBTI) in p-MOSFETs with Ultra-Thin Gate Oxide |
| Abstract |
A. Suzuki,
K. Tabuchi, H. Kimura, T. Hasegawa, S. Kadomura,
K. Kakamu*, H. Kudo**, M. Kawano**, A. Tsukune**
and M. Yamada**, Sony Corporation, Kanagawa,
Japan, *Fujitsu VLSI Ltd., Mie-ken, Japan and
**Fujitsu Ltd., Mie-ken, Japan |
3:50pm |
22.2 |
New
Guideline for Hydrogen Treatment in Advanced
System LSI |
| Abstract |
E. Morifuji,
T. Kumamori, M. Muta, K. Suzuki, M.S. Krishnan*,
T. Brozek*, X. Li*, W. Asano, M. Nishigori, N.
Yanagiya, S. Yamada, K. Miyamoto, T. Noguchi and
M. Kakumu, Toshiba Corporation, Yokohama,
Japan and *PDF Solutions, Inc., San Jose, CA |
4:15pm |
22.3 |
The
Effects of Substrate Coupling on Triggering
Uniformity and ESD Failure Threshold of Fully
Silicided NMOS Transistors |
| Abstract |
Y.J. Huh, V.
Axerad*, J.-W. Chen and P. Bendix, LSI Logic
Corp., Milpitas, CA and *Sequoia Design Systems,
Woodside, CA |
4:40pm |
22.4 |
Re-Defining
Reliability Assessment Per New Intra-Via Cu
Leakage Degradation |
| Abstract |
W.S. Song,
C.S. Lee, K.C. Park, B.S. Suh, J.W. Kim, S.Y.
Kim, Y.J. Wee, S.M. Choi, H.-K. Kang, S.U. Kim
and K.P. Suh, Samsung Electronics, Co., Ltd.,
Kyongki-Do, Korea |
|
