2006 VLSI Circuits Technical Program


Welcome to the 2006 Symposium
on VLSI Circuits



You are cordially invited to attend the 2006 Symposium on VLSI Circuits, to be held on June 15-17th, 2006, at the Hilton Hawaiian Village in Honolulu, Hawaii. Following the tradition of the last several years, the Symposium on VLSI Circuits will follow the Symposium on VLSI Technology at the same location.

Starting in 1987, this year marks the 20th annual Symposium on VLSI Circuits. The Symposium has established itself as a major international forum for presenting and exchanging important ideas and new developments in VLSI circuit design. The scope of the conference includes new concepts in VLSI, novel Memory technologies, Analog Circuits, Analog/Digital Conversion, Digital Processing, Static and Dynamic Memory, Signal Processing, I/O and Communication circuits. Contributions to the Symposium come from both industry and academia, from around the world.

New for this year, preceding the Symposium on June 14th, two all-day Short Courses on VLSI circuits will be held. For one registration fee, participants can attend either parallel course. The first focusing on new challenges facing digital designers titled; “Designing for Paradigm Shifts in Microprocessors and Networking”, the other choice focuses on the increasing challenges of Analog and Digital conversion in advanced technologies titled; “Data Converter Design for Embedded Systems”.

This year, the technical program committee reviewed 412 papers, selecting 113 outstanding papers for presentation. These papers disclose new and interesting design concepts for memory, processor, communication, analog, and signal processing circuits, and represent the leading edge of VLSI circuit design.

We have invited four distinguished speakers to describe recent advances and new challenges related to VLSI circuits, technology and applications: “High Performance Processors in a Power Limited World”, “Finger-Vein Authentication Technology and its Future”, “Analog and The Big Bang: A Universal Model for Mixed Signal VLSI Trends”, “Through Silicon Via and 3-D Wafer/Chip Stacking Technology”.

To complement the formal talks, we have arranged three evening rump sessions on interesting and provocative subjects to give you an opportunity to participate in the discussions and mix with the participants who were chosen to represent contrasting opinions on the topics. The rump sessions explore: “What will be the next embedded memory workhorse?”; “Power management: What are the device and circuit trade-offs and how will it be managed at 45nm and 32nm nodes”; “Complete integration of SoC power management - reality or mirage?”.

The rich technical content of the program will undoubtedly interest you, and we certainly hope that the Symposium will be a fruitful and enjoyable experience.

This booklet contains the advance program together with forms for the Symposium registration and hotel reservations. Please try to complete and return these forms as soon as possible. Although the on-site registration will be available at the conference, pre-registration will facilitate Symposium planning.

We look forward to meeting with you at the Symposium in Honolulu.



Stephen V. Kosonocky

Kazuo Yano
Program Chair Program Co-Chair

To download a PDF of the Circuits Program - click here


CONFERENCE SCHEDULE


Tuesday, June 13

7:30am-5:30p

Registration
Wednesday, June 14
7:30am-5:00p Registration
8:10a-5:30p Short Course
6:00p-8:00p Reception
8:00p-10:00p Technology and Circuits Joint Rump Session
Thursday, June 15
7:30a-5:00p Registration
8:00a-9:45p Session 1 Welcome and Plenary Session I
10:00a-12:05p Session 2 SRAM Cell Stability
Session 3 Image Sensors
Session 4 Clock Generation for High Speed Transceivers
1:30p-3:10p
Session 5 RF Blocks for Tuners and Sensor Networks
Session 6 Data Converter Techniques
Session 7 Real World Interfaces
3:25p-5:30pSession 8 On-Chip Environment and Process Monitoring
Session 9 Serial Link Transceivers
Session 10 Analog Techniques
8:00p-10:00p Rump Sessions
Friday, June 16 7:30a-5:00p Registration
8:00a-9:30a Session 11 Plenary Session II
9:45a-11:50a Session 12 Clock Generation and Distribution
Session 13 Non-Volatile Memory Architecture and Circuits
Session 14 Serial Receivers
1:30p-3:10p Session 15 SRAM Architecture and Techniques
Session 16 Nyquist ADC I
Session 17 MM-Wave
3:25p-5:30pSession 18 Digital Processing
Session 19 Oversampled ADCs
Session 20 Oscillators and Dividers
7:00p-9:00p Circuits Symposium Banquet
Saturday, June 17 7:30a-5:00p Registration
8:30a-10:35ap
Session 21 Advanced Memory and Circuits
Session 22 Equalization Techniques
Session 23 UWB
10:50a-12:55p
Session 24 Reducing Power, Noise, and Leakage
Session 25 Nyquist ADCs II
Session 26 RF Front Ends and Baseband Processing


line