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Press Kit

The following press materials are available for pre-conference publicity for the 2016 Symposia on VLSI Technology & Circuits

Press Releases

VLSI Symposia 2016 luncheon presentation –June 2, 2016

VLSI Symposia 2016 circuits plenary sessions (English) – May 18, 2016

VLSI Symposia 2016 technology plenary sessions (English) – May 18, 2016

VLSI Symposia 2016 technology short courses (English) – May 11, 2016

VLSI Symposia 2016 executive panel session – May 10, 2016

VLSI Symposia 2016 circuits short courses (English) – May 9, 2016

VLSI Symposia 2016 technical terms (Korean) – April 20, 2016

VLSI Symposia 2016 technical tipsheet (Korean) – April 20, 2016

VLSI Symposia 2016 technical terms (Japanese) – April 20, 2016

VLSI Symposia 2016 technical tipsheet (Japanese) – April 20, 2016

VLSI Symposia 2016 lead release (Japanese) – April 20, 2016

VLSI Symposia 2016 technical terms (English) – April 20, 2016

VLSI Symposia 2016 technical tipsheet (English) – April 20, 2016

VLSI Symposia 2016 lead release (English) – April 20, 2016

VLSI Symposia 2016 evening panel release (English) – April 5, 2016

VLSI Symposia 2016 theme release (English) – March 23, 2016

VLSI Symposia 2016 theme release (Japanese) – March 23, 2016

VLSI Symposia 2016 theme release (Chinese) – March 23, 2016

VLSI Symposia 2016 Call for late news papers release (English) – March 1, 2016

VLSI Symposia 2016 Call for papers (second) release (English) – January 18, 2016

VLSI Symposia 2016 Call for papers release (English) – September 28, 2015

 

 

 

 

 

 

 

 

 

 

 

Images

Hilton Hawaiian Village Venue

2016 VLSI Symposium Technology logo

2016 VLSI Symposium Circuits logo

Professor Dr. Subramanian Iyer of UCLA’s Electrical Engineering Department

Technology Plenary Session 1 – Stephen Lloyd, InvenSense, Inc.

Technology Plenary Session 2 – Takao Asami, Nissan

Circuits Plenary Session 1 – Olivier Temam, Google

Circuits Plenary Session 2 – Tetsuo Nomoto, Sony

2016 VLSI Paper T2.1, Figure 7, Si FinFET-based 10nm Technology with Multi Vt Gate Stack for Low Power and High Performance Applications

2016 VLSI Paper T2.2, Figure 8, FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond

2016 VLSI Paper T2.3, Figure 2, High Performance In0.53Ga0.47As FinFETs Fabricated on 300mm Si Substrate

2016 VLSI Paper T2.3, Figure 14, High Performance In0.53Ga0.47As FinFETs Fabricated on 300mm Si Substrate

2016 VLSI Paper T2.4, Figures 12 & 13, Achieving Sub-ns Switching of STT-MRAM for Future Embedded LLC Applications Through Improvement of Nucleation and Propagation Switching Mechanisms

2016 VLSI Paper T9.1, Figure 15, Demonstration of a Sub-0.03 um2 High Density 6-T SRAM with Scaled Bulk FinFETs for Mobile SOC Applications Beyond 10nm Node

2016 VLSI Paper T9.3, Figure 2, Replacement High-K/Metal-Gate High-Ge-Content Strained SiGe FinFETs with High Hole Mobility and Excellent SS and Reliability at Aggressive EOT ~7Å and Scaled Dimensions Down to Sub-4nm Fin Widths

2016 VLSI Paper T9.3, Figure 3, Replacement High-K/Metal-Gate High-Ge-Content Strained SiGe FinFETs with High Hole Mobility and Excellent SS and Reliability at Aggressive EOT ~7Å and Scaled Dimensions Down to Sub-4nm Fin Widths

2016 VLSI Paper T12.4, Figure 5, A Novel Low Power Phase Change Memory Using Inter-Granular Switching

2016 VLSI Paper T14.2, Figure 14, Sub-3ns Pulse with Sub-100µA Switching of 1x-2xnm Perpendicular MTJ for High-Performance Embedded STT-MRAM Towards Sub-20nm CMOS

2016 VLSI Paper T15.1, Figure 2, Gate-All-Around MOSFETs Based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates

2016 VLSI Paper T17.3, Figures 1 & 2, First Demonstration of a CMOS-Over-CMOS 3D VLSI CoolCube™ Integration on 300mm Wafers

2016 VLSI Paper T18.2, Figure 1, Four-Layer 3D Vertical RRAM Integrated with FinFET as a Versatile Computing Unit for Brain-Inspired Cognitive Information Processing

2016 VLSI Paper T18.2, Figure 6, Four-Layer 3D Vertical RRAM Integrated with FinFET as a Versatile Computing Unit for Brain-Inspired Cognitive Information Processing

2016 VLSI Paper T21.1, Figure 9, Enabling High-Performance Heterogeneous TFET/CMOS Logic with Novel Circuits Using TFET Unidirectionality and Low-VDD Operation

2016 VLSI Paper T21.1, Figure 10, Enabling High-Performance Heterogeneous TFET/CMOS Logic with Novel Circuits Using TFET Unidirectionality and Low-VDD Operation

2016 VLSI Paper C8.1, Figure 12, An Energy Harvesting Wireless Sensor Node for IoT Systems Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14nm Tri-Gate CMOS

2016 VLSI Paper C8.4, Figure 6, Multi-modal Smart Bio-sensing SoC Platform with >80dB SNR 35µA PPG RX Chain

2016 VLSI Paper C7.1, Figure 1, A Bluetooth Low-Energy (BLE) Transceiver with TX/RX Switchable On-Chip Matching Network, 2.75mW High-IF Discrete-Time Receiver, and 3.6mW All-Digital Transmitter

2016 VLSI Paper C12.2, Figure 5, Embedded Memory and ARM Cortex-M0 Core Using 60nm C-Axis Aligned Crystalline Indium–Gallium–Zinc Oxide FET Integrated with 65nm Si CMOS

2016 VLSI Paper C21.1, Figure 4, An 8.3M-pixel 480fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and 2-on-1 Stacked Device Structure

2016 VLSI Paper T22.4, Figure 1 – Novel Pixel Structure with Stacked Deep Photodiode to Achieve High NIR Sensitivity and High MTF

2016 VLSI Paper C8.2, Figure 2, Lensless Smart Sensors: Optical and Thermal Sensing for the Internet of Things

2016 VLSI Paper C5.4, Figure 8, A 56Gb/s PAM4 Wireline Transceiver using a 32-way Time-Interleaved SAR ADC in 16nm FinFET

2016 VLSI Paper C17.1, Figure 8, A 0.3-2.6 TOPS/W Precision-Scalable Processor for Real-Time Large-Scale ConvNets

2016 VLSI Paper C4.4, Figure 1, A Front-end ASIC with Receive Sub-Array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

2016 VLSI Paper C8.3, Figure 1, Features of Retinal Prosthesis Using Suprachoroidal Transretinal Stimulation from an Electrical Circuit Perspective

2016 VLSI Paper T20.4, Figure 2, Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable µ-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits

PRESS REGISTRATION

Registration at the 2016 Symposia on VLSI Technology & Circuits is complimentary for the press. Whether you would like to do a news story, conference preview or an in-depth exploration of a particular technology, please contact one of us for the additional information or interviews you may need.

Register Now

If you plan to attend, please contact us; or print out the registration page with your contact information, write “Press” on it, and fax or mail it to Conference Manager Phyllis Mahoney, 19803 Laurel Valley Place, Montgomery Village, MD 20886, USA; tel. +1-301-527-0900, ext. 2; fax +1 527-0994. Phyllis also can be reached by email with any registration/attendance questions at phyllism@widerkehr.com.

Be prepared to show a business card when you arrive at the Symposia.

Editor Contact

Chris Burke
Media Relations Director
+1 919-872-8172
chris.burke@btbmarketing.com

Phyllis Mahoney
Conference Manager
+1 301-527-0900
phyllism@widerkehr.com
© 2016 VLSI Symposium. All Rights Reserved.
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