Welcome to the 2001 Symposium on VLSI Technology
On behalf of the organizing Committees, you are cordially invited to attend the 2001 Symposium on VLSI Technology to be held from June 12-14 in Kyoto, Japan.
This symposium has established itself as one of the most important international forums for presenting the latest research and developments in the area of VLSI and
ULSI technologies and their applications. This year in the beginning of the 21st century, the symposium opens up a new feature on its 21 year tradition. We selected
69 very high quality papers from 170 contributed papers submitted from all over the world, and organized them into 18 sessions. We are also delighted to have two distinguished
Invited Speakers for the Plenary Session. Dr. A. Koike, Tresenti Technologies, will speak on "Manufacturing in 21st Century-New Concept for 300mm Fab.", and Dr. R. Camposano, Synopsys, will address "Technology Needs for System on Chip Design".
Four Rump Sessions are planned for the evening as a means to facilitate informal discussions among the researchers. Three of the four are regular sessions, and will cover specific technology related topics of timely interest;
| 1) |
High-K Gate Dielectrics: Is It Necessary ? If So, When, What, How ? |
| 2) |
Extending Copper/low k Interconnects to 100 nm and Beyond: How "Low" Can We Go ? Are There Any Alternative Approaches ? |
| 3) |
Technology Challenges and Solutions for Scaling Flash Memory-What Do the Next Ten Years Promise ? |
The other one is a Joint Session with the Symposium on VLSI Circuits which will address "Which Features of an IC Technology will Benefit Radio SOC ?".
A one-day Short Course, scheduled for Monday June 11, will cover "The Key Aspects for System-on-a-Chip". This should be an excellent opportunity for experienced as well as new engineers to broaden their technical base.
The symposium registration fee covers all of the sessions including the Rump Sessions. Coffee breaks and the dinner are also included. Registration for the Short Course is extra. The detailed registration fees and hotel reservation schedules are
included in this web site.
As in past years, we expect a strong participation from leaders of VLSI industry and academic researchers. We look forward to an exciting Symposium in Kyoto. Please join us. |
Tadashi Nishimura |
Yuan Taur |
| Program Chair |
Program Co-Chair |
CONFERENCE SCHEDULE
Sunday, June 10 |
18:00-20:00 |
Registration |
| Monday, June 11 |
7:00 |
Breakfast [Suzaku] |
| 8:00 |
Registration |
| 8:55-12:15 |
Short Course [Shunju] |
| 13:45-17:00 |
Short Course [Shunju] |
| 18:00-20:00 |
Reception [Suzaku] |
| Tuesday, June 12 |
7:00 |
Breakfast [Suzaku] |
| 8:00 |
Registration |
8:20-9:55 |
Session 1 |
Welcome and Plenary Session [Shunju] |
| 10:10-12:15 |
Session 2 |
Highlights [Shunju] |
| 13:30-15:10 |
Session 3A |
Advanced CMOS Front End Technology [Shunju] |
| Session 3B |
DRAM Technology I [Suzaku] |
| 15:30-16:45 |
Session 4A |
Sub 50nm CMOS and Advanced Lithography [Shunju] |
| Session 4B |
DRAM Capacitor [Suzaku] |
| 18:30-20:30 |
Dinner [Shunju] |
| Wednesday, June 13 |
7:00 |
Breakfast [Suzaku, Salon de Charme] |
| 8:30-10:10 |
Session 5A |
Advanced Gate Stack I [Shunju I] |
| Session 5B |
Novel Device Technology [Shunju II] |
| 10:30-12:10 |
Session 6A |
Advanced Gate Stack II [Shunju I] |
| Session 6B |
SOI Device Technology [Shunju II] |
| 13:30-15:10 |
Session 7A |
Gate Dielectric Technology [Shunju I] |
| Session 7B |
RF & Analog Device Technology [Shunju II] |
| 15:30-17:10 |
Session 8A |
Gate Dielectric Reliability [Shunju I] |
| Session 8B |
SoC Integration [Shunju II] |
| 20:00-22:00 |
Rump Sessions [Suzaku, Momiji, Matsu, Sakura] |
| Thursday, June 14 |
7:00 |
Breakfast [Salon de Charme, Kitayamasugi] |
| 8:30-9:45 |
Session 9A |
Nonvolatile Memory Technology [Shunju I] |
| Session 9B |
CMOS Reliability [Shunju II] |
| 10:05-11:45 |
Session 10 |
DRAM Technology II [Shunju I] |
| 13:15-14:55 |
Session 11 |
High-k Gate Dielectrics [Shunju I] |
| 15:15-16:55 |
Session 12 |
Multilevel Interconnects [Shunju I] |
PROGRAM
Session 1 |
Welcome and Plenary Session [Shunju] |
| Chairpersons |
T. Nishimura, Mitsubishi Electric
Y. Taur, IBM |
8:20 |
1-1 |
Welcome and Opening Remarks |
| |
E. Takeda, C. Lage |
| hitachi, motorola |
8:35 |
1-2 |
Manufacturing in 21st Century-New Concept for 300mm Fab (Invited) |
| |
A. Koike |
| Trecenti Technologies, Japan |
9:15 |
1-3 |
Design Technology for Systems on a Chip (Invited) |
| |
R. Camposano |
| Synopsys, USA |
Session 2 |
Highlights [Shunju] |
| Chairpersons |
T. Kunio, NEC
C.-S. Pai, Agere Systems |
10:00 |
2-1 |
Highly Manufacturable and High Performance SDR/DDR 4Gb DRAM |
| Abstract |
K.N. Kim, H.S. Jeong, W.S. Yang, Y.S. Hwang, C.H. Cho, M.M. Jeong,
S. Park, S.J. Ahn, Y.S. Chun, S.H. Shin, J.S. Park, S.H. Song, J.Y. Lee, S.M. Jang, C.H. Lee, J.H. Jeong, M.H. Cho, H.I.
Yoon and J.S. Jeon |
| Samsung Electronics Co., Korea |
10:35 |
2-2 |
Scaling Towards 35nm Gate Length CMOS |
| Abstract |
B. Yu, H. Wang, Q. Xiang, J.X. An, J. Jeon and M.-R. Lin |
| Advanced Micro Devices, Inc., USA |
11:00 |
2-3 |
A High Performance 100 nm Generation SOC Technology [CMOS IV]
for High Density Embedded Memory and Mixed Signal LSIs |
| Abstract |
K. Miyashita, T. Nakayama, A. Oishi, R. Hasumi, M. Owada, S. Aota, Y. Okayama, M. Matsumoto, H. Igarashi, T. Yoshida, K. Kasai, T. Yoshitomi, Y. Fukaura, H. Kawasaki, K. Ishimaru, K. Adachi, M. Fujiwara, K. Ohuchi, M. Takayanagi, H. Oyamatsu, F. Matsuoka, T. Noguchi and M. Kakumu |
| Toshiba Corporation, Japan |
11:25 |
2-4 |
Barrier-metal-free (BMF), Cu Dual-damascene Interconnects
with Cu-epi-contacts buried in Anti-diffusive, Low-k Organic film |
| Abstract |
M. Tada, H. Ohtake, T. Harada, M. Hiroi, S. Saito, T. Onodera,
N. Furutake, J. Kawahara, M. Tagami, K. Kinoshita, T. Fukai,
T. Mogami and Y. Hayashi |
| NEC Corporation, Japan |
11:30 |
2-5 |
High-Quality Ultra-thin HfO2 Gate Dielectric
MOSFETs with TaN Electrode and Nitridation Surface Preparation |
| Abstract |
R. Choi, C.S. Kang, B.H. Lee, K. Onishi, R. Nieh, S. Gopalan,
E. Dharmarajan and J.C. Lee |
| The University of Texas at Austin, USA |
Session 3A |
Advanced CMOS Front End Technology [Shunju] |
| Chairpersons |
S. Kawamura, Fujitsu
S. Thompson, Intel |
13:30 |
3A-1 |
Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub-50nm Gate Length CMOS Devices |
| Abstract |
T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi and M. Bohr |
| Intel Corporation, USA |
13:55 |
3A-2 |
Ultra-Thin Body PMOSFETs with Selectively Deposited Ge Source/Drain |
| Abstract |
Y.-K. Choi, D. Ha, T.-J. King and C. Hu |
| University of California, USA |
14:20 |
3A-3 |
Shallow n+/p+ junction formation using plasma immersion ion implantation for CMOS Technology |
| Abstract |
K. Lee, J.-H. Sim*, Y. Li*, W.-T. Kang, R. Malik, R. Rengarajan, S. Chaloux*, J. Bernstein** and P. Kellerman** |
| Infineon Technologies Corp., *IBM Microelectronics Semiconductor R&D Center and **Axcelis Technologies, USA |
14:45 |
3A-4 |
High Performance Sub-50nm CMOS with Advanced Gate Stack |
| Abstract |
Q. Xiang, B. Yu, H. Wang and M.-R. Lin |
| Advanced Micro Devices, Inc., USA |
Session 3B |
DRAM Technology I [Suzaku] |
| Chairpersons |
D.-H. Lee, Hyundai Micro Electronics
C. Dennison, Ovonyx |
13:30 |
3B-1 |
A 0.115µm² 8F2 DRAM working cell with LPRD(Low_Prasitic_Resistance Device) and poly metal gate Technology for Gigabit DRAM |
| Abstract |
H. Noh, W. Cho, G. Jeong, M. Huh, J. Ahn,
Y. Kim, S. Jeong, S. Lee, D. Kim, H. Kim,
J. Suh, J. Park, S. Lee and H. Yoon |
| Hyundai Electronics Co., LTD, Korea |
13:55 |
3B-2 |
A Strategy for Long Data Retention Time of 512Mb DRAM with 0.12µm Design Rule |
| Abstract |
H.S. Uh, J.K. Lee, S.H. Lee, Y.S. Ahn,
H.O. Lee, S.H. Hong, J.W. Lee, G.H. Koh,
G.T. Jeong, T.Y. Chung and K. Kim |
| Samsung Electronics Co., Korea |
14:20 |
3B-3 |
A 0.15µm Logic based embedded DRAM technology featuring 0.425µm² Stacked Cell using MIM (Metal-Insulator-Metal) Capacitor |
| Abstract |
M. Takeuchi, K. Inoue, M. Sakao, T. Sakoh,
T. Kitamura, S. Arai, T. Iizuka, T. Yamamoto, H. Shirai, Y. Aoki, M. Hamada, R. Kubota and S. Kishi |
| NEC Corporation, Japan |
14:45 |
3B-4 |
W/WN/Poly gate implementation for sub-130nm vertical cell DRAM |
| Abstract |
R. Malik, L. Clevenger*, I. McStay, O. Gluschenkov*, W. Robl, P. Shafer*, G. Stojakovic, W. Yan*, M. Naeem*, R. Ramachandran, K. Wong*, J. Prakash, W. Kang, Y. Li*, R. Vollertsen**, A. Strong**, W. Bergner, R. Divakaruni* and G. Bronner* |
| Infineon Technologies Corp., *IBM Microelectronics Semiconductor R&D Center and **IBM Microelectronics, USA |
Session 4A |
Sub 50nm CMOS and Advanced Lithography [Shunju] |
| Chairpersons |
J. Ida, Oki Electric
J. Watt, Cypress Semiconductor |
15:30 |
4A-1 |
A Manufacturable 25nm Planar MOSFET Technology |
| Abstract |
Y.V. Ponomarev, J.J.G.P. Loo, C.J.J. Dachs, F.N. Cubaynes, M.A. Verheijen*, M. Kaiser*, J.G.M. van Berkum*, S. Kubicek**, J. Bolk*** and M. Rovers |
| Philips Research Leuven, Belgium, *Philips Research, The Netherlands, **IMEC, Belgium and ***Philips Semiconductors, The Netherlands |
15:55 |
4A-2 |
Experimental and Simulation Study on Sub-50 nm CMOS Design |
| Abstract |
S. Pidin, H. Shido, T. Yamamoto, N. Horiguchi, H. Kurata and T. Sugii |
| Fujitsu Laboratories Ltd., Japan |
16:20 |
4A-3 |
High-Performance 157 nm Resist based on Fluorine-Containing Polymer |
| Abstract |
S. Kishimura, M. Endo and M. Sasago |
| Matsushita Electronics Corporation, Japan |
Session 4B |
DRAM Capacitor [Suzaku] |
| Chairpersons |
T. Eimori, Mitsubishi Electric
D. Shum, Infineon Technologies |
15:30 |
4B-1 |
Oxidation-Resistant Amorphous TaN Barrier for MIM-Ta2O5 Capacitors in Giga-Bit DRAMs |
| Abstract |
Y. Nakamura, I. Asano, M. Hiratani*, T. Saito* and H. Goto |
| ELPIDA MEMORY, Inc. and *Hitachi, Ltd., Japan |
15:55 |
4B-2 |
A Heteroepitaxial MIM-Ta2O5 Capacitor with Enhanced Dielectric Constant for DRAMs of G-bit Generation and beyond |
| Abstract |
M. Hiratani, T. Hamada, S. Iijima*, Y. Ohji,
I. Asano*, N. Nakanishi* and S. Kimura |
| Hitachi Ltd. and *Elpida Memory, Inc., Japan |
16:20 |
4B-3 |
Cylindrical Ru / SrTiO3 / Ru Capacitor Technology for 0.11µm Generation DRAMs |
| Abstract |
C.M. Chu, M. Kiyotoshi*, S. Niwa*, J. Nakahira**, K. Eguchi*, S. Yamazaki*, K. Tsunoda***, M. Fukuda***, T. Suzuki**, M. Nakabayashi**, H. Tomita*, C.M. Shiah, D. Matsunaga** and K. Hieda* |
| Winbond Electronics Corporation, *Toshiba Corporation, **Fujitsu Limited and ***Fujitsu Laboratories Limited, Japan |
Session 5A |
Advanced Gate Stack I [Shunju I] |
| Chairpersons |
K. Shibahara, Hiroshima Univ.
P. Zeitzoff, SEMATECH |
8:30 |
5A-1 |
Metal Gate Work Function Adjustment for Future CMOS Technology |
| Abstract |
Q. Lu, R. Lin, P. Ranade, T.-J. King and C. Hu |
| University of California, USA |
8:55 |
5A-2 |
Electrical Characteristics of TaSixNy Gate Electrodes For Dual Gate Si-CMOS Devices |
| Abstract |
Y.-S. Suh, G. Heuss, H. Zhong, S.-N. Hong and V. Misra |
| North Carolina State University, USA |
9:20 |
5A-3 |
Effects of High-k Dielectrics on the Workfunctions of Metal and Silicon Gates |
| Abstract |
Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King and C. Hu |
| University of California, USA |
9:45 |
5A-4 |
Electron Wavefunction Penetration into Gate Dielectric and Interface Scattering- An Alternative to Surface Roughness Scattering Model |
| Abstract |
I. Polishchuk and C. Hu |
| University of California, USA |
Session 5B |
Novel Device Technology [Shunju II] |
| Chairpersons |
S.S. Chung, National Chiao Tung Univ.
M.-R. Lin, AMD |
8:30 |
5B-1 |
Fabrication of a Novel Vertical pMOSFET with Enhanced Drive Current and Reduced Short-Channel Effects and Floating Body Effects |
| Abstract |
Q. Ouyang, X. Chen*, A.F. Tasch*, L.F. Register*, S.K. Banerjee*, J.O. Chu and J.A. Ott |
| IBM T.J. Watson Research Center and *University of Texas at Austin, USA |
8:55 |
5B-2 |
High performance 40 nm vertical MOSFET within a conventional CMOS process flow |
| Abstract |
E. Josse, T. Skotnicki, M. Jurczak*, M. Paoli,
B. Tormen, D. Dutartre, P. Ribot*, A. Villaret and E. Sondergard |
| STMicroelectronics and *France Telecom R&D, France |
9:20 |
5B-3 |
Carrier Mobility Enhancement in Strained Si-On-Insulator Fabricated by Wafer Bonding |
| Abstract |
L.-J. Huang, J.O. Chu, S. Goma, C.P. DÕEmic, S.J. Koester, D.F. Canaperi, P.M. Mooney,
S.A. Cordes, J.L. Speidell, R.M. Anderson and H.-S.P. Wong |
| IBM Thomas J. Watson Research Center, USA |
9:45 |
5B-4 |
Strained Si NMOSFETs for High Performance CMOS Technology |
| Abstract |
K. Rim, S. Koester, M. Hargrove*, J. Chu, P.M. Mooney, J. Ott, T. Kanarsky*, P. Ronsheim*, M. Ieong*, A. Grill and H.-S.P. Wong |
| IBM T.J. Watson Research Center and *IBM Microelectronics Division, USA |
Session 6A |
Advanced Gate Stack II [Shunju I] |
| Chairpersons |
T. Hiramoto, Univ. of Tokyo
S. Broydo, Applied Materials |
10:30 |
6A-1 |
Ge-Redistributed Poly-Si/SiGe Stack Gate (GRPSG) for High-Performance CMOSFETs |
| Abstract |
H.S. Rhee, G.J. Bae, T.H. Choe, S.S. Kim, S. Song, N.I. Lee, K. Fujihara, H.K. Kang and J.T. Moon |
| Samsung Electronics Co., Ltd., Korea |
10:55 |
6A-2 |
Performance Improvement of Metal Gate CMOS Technologies |
| Abstract |
S. Matsuda, H. Yamakawa, A. Azuma and Y. Toyoshima |
| Toshiba Corporation Semiconductor Company, Japan |
11:20 |
6A-3 |
Novel Damage-free Direct Metal Gate Process Using Atomic Layer Deposition |
| Abstract |
D.-G. Park, K.-Y. Lim, H.-J. Cho, T.-H. Cha,
J.-J. Kim, J.-K. Ko, I.-S. Yeo and J.W. Park |
| Hyundai Electronics Industries Co. Ltd., Korea |
11:45 |
6A-4 |
Low Resistivity bcc-Ta/TaNx Metal Gate MNSFETs Having Plane Gate Structure Featuring Fully Low-Temperature Processing below 450¡C |
| Abstract |
H. Shimada, I. Ohshima, S. Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa and T. Ohmi |
| Tohoku University, Japan |
Session 6B |
SOI Device Technology [Shunju II] |
| Chairpersons |
Y. Omura, Kansai Univ.
J. Woo, Univ. of California |
10:30 |
6B-1 |
50nm SOI CMOS Transistors with Ultra Shallow Junction using Laser Annealing and Pre-Amorphization Implantation |
| Abstract |
C. Park, S.-D. Kim, Y. Wang*, S. Talwar* and J.C.S. Woo |
| University of California and *Verdant Technologies, USA |
10:55 |
6B-2 |
High Performance sub-60 nm SOI MOSFETs with 1.2 nm Thick Nitride/Oxide Gate Dielectric |
| Abstract |
W.P. Maszara, S. Krishnan, Q. Xiang and M.-R. Lin |
| Advanced Micro Devices, USA |
11:20 |
6B-3 |
Impact of CMOS process scaling and SOI on the soft error rates of logic processes |
| Abstract |
S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta and C. Dai |
| Intel Corporation, USA |
11:45 |
6B-4 |
Effects of Gate-to-Body Tunneling Current on PD/SOI CMOS SRAM |
| Abstract |
R.V. Joshi, C.T. Chuang, S.K.H. Fung*, F. Assaderaghi*, M. Sherony*, I. Yang* and G. Shahidi* |
| IBM T.J. Watson Research Center and *IBM SRDC, U.S.A. |
Session 7A |
Gate Dielectric Technology [Shunju I] |
| Chairpersons |
M. Ohkura, Hitachi
J. Lee, Univ. of Texas |
13:30 |
7A-1 |
Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide |
| Abstract |
H.S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi and H. Iwai* |
| Toshiba Corporation and *Tokyo Institute of Technology, Japan |
13:55 |
7A-2 |
A Multi-gate Dielectric Technology Using Hydrogen Pre-treatment for 100nm generation System-on-a-Chip |
| Abstract |
A. Ono, K. Fukasaku, T. Hirai, M. Makabe, S. Koyama, N. Ikezawa, K. Ando, T. Suzuki, K. Imai and N. Nakamura |
| NEC Corporation, Japan |
14:20 |
7A-3 |
Controlling Base-SiO2 Density of Low-Leakage 1.6nm Gate-SiON for High-Performance and Highly Reliable n/pFETs |
| Abstract |
M. Togo, K. Watanabe, M. Terai, S. Kimura, A. Morioka, T. Yamamoto, T. Tatsumi and T. Mogami |
| NEC Corporation, Japan |
14:45 |
7A-4 |
Radical Nitridation in Multi-oxide Process for 100nm Generation CMOS Technology |
| Abstract |
Y. Yasuda, N. Kimizuka, K. Watanabe, T. Tatsumi, A. Ono, K. Fukasaku, K. Imai and N. Nakamura |
| NEC Corporation, Japan |
Session 7B |
RF & Analog Device Technology [Shunju II] |
| Chairpersons |
H. Kuroda, Sony
B. Zhao, Conexant Systems |
13:30 |
7B-1 |
A 0.13-µm SOI CMOS Technology for Low-power Digital and RF Applications |
| Abstract |
N. Zamdmer, A. Ray, J.-O. Plouchart*, L. Wagner, N. Fong**, K.A. Jenkins*, W. Jin, P. Smeys, I. Yang, G. Shahidi and F. Assaderaghi |
| IBM Semiconductor Research and Development Center (SRDC), *IBM T.J. Watson Research Center, USA and **Carleton University, Canada |
13:55 |
7B-2 |
SPEECHDeep Sub-Micron CMOS device design for Low Power Analog Applications_TITLE |
| Abstract |
H.V. Deshpande, B. Cheng* and J.C.S. Woo |
| University of California and *Motorola, USA |
14:20 |
7B-3 |
Investigations of Bulk Dynamic Threshold-Voltage MOSFET with 65GHz "Normal-Mode" Ft and 220GHz "Over-Drive Mode" Ft for RF Applications |
| Abstract |
C.-Y. Chang, J.-G. Su, H.-M. Hsu*, S.-C. Wong*, T.-Y. Huang and Y.-C. Sun* |
| National Chiao-Tung University and *Taiwan Semiconductor Manufacturing Co., Taiwan, R.O.C. |
14:45 |
7B-4 |
A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides |
| Abstract |
T. Ohguro, T. Nagano, M. Fujiwara, M. Takayanagi, T. Shimizu, H.S. Momose, S. Nakamura and Y. Toyoshima |
| Toshiba Corp., Japan |
Session 8A |
Gate Dielectric Reliability [Shunju I] |
| Chairpersons |
H. Hanafusa, Sanyo Electric
Y. Ponomarev, Philips Research |
15:30 |
8A-1 |
Transistor-Limited Constant Voltage Stress of Gate Dielectrics |
| Abstract |
B.P. Linder, D.J. Frank, J.H. Stathis and S.A. Cohen |
| IBM Research Division, USA |
15:55 |
8A-2 |
Statistical Analysis of Soft Breakdown in Ultrathin Gate Oxides |
| Abstract |
W. Mizubayashi, Y. Yoshida, S. Miyazaki and M. Hirose |
| Hiroshima University, Japan |
16:20 |
8A-3 |
A New Quantitative Hydrogen-Based Model for Ultra-Thin Oxide Breakdown |
| Abstract |
J. Sune and E. Wu* |
| Universitat Autonoma de Barcelona, SPAIN and *IBM Microelectronics Division, USA |
16:45 |
8A-4 |
Gate Voltage Dependent Model for TDDB Lifetime Prediction under Direct Tunneling Regime |
| Abstract |
M. Takayanagi, S. Takagi and Y. Toyoshima |
| Toshiba Corporation, Japan |
Session 8B |
SoC Integration [Shunju II] |
| Chairpersons |
F. Matsuoka, Toshiba Semiconductor Company
S. Yeh, LSI Logic |
15:30 |
8B-1 |
A 0.13µm CMOS Platform with Cu/ Low-k Interconnects for System On Chip Applications |
| Abstract |
T. Schiml, S. Biesemans*, G. Brase, L. Burrell*, A. Cowley, K.C. Chen**, A.v. Ehrenwall, B.v. Ehrenwall, P. Felsner, J. Gill*, F. Grellner, F. Guarin*, L.K. Han*, M. Hoinkis, E. Hsiung**, E. Kaltalioglu, P. Kim*, G. Knoblinger, S. Kulkarni*, A. Leslie, T. Mono, T. Schafbauer, U. Schroeder,K. Schruefer, T. Spooner*, D.Warner, C. Wang**, R. Wong*, E. Demm, P. Leung**, M. Stetter, C. Wann*, J.K. Chen** and E. Crabb** |
| Infineon Technologies, *IBM and **UMC, USA |
15:55 |
8B-2 |
A High Performance 0.12µm CMOS with Manufacturable 0.18µm Technology |
| Abstract |
K. Ichinose, T. Saito, Y. Yanagida, Y. Nonaka, K. Torii, H. Sato, N. Saito*, S. Wada, K. Mori and S. Mitani |
| Hitachi, Ltd. and *Hitachi ULSI Systems Co., Ltd., Japan |
16:20 |
8B-3 |
High-Density and High-Performance 6T-SRAM for System-on-Chip in 130 nm CMOS Technology |
| Abstract |
W. Kong, R. Venkatraman, R. Castagnetti, F. Duan and S. Ramesh |
| LSI Logic Corporation, USA |
16:45 | Masakazu
8B-4 |
Scalability and Biasing Strategy for CMOS with Active Well Bias |
| Abstract |
S.-F. Huang, C. Wann, Y.-S. Huang*, C.-Y. Lin*, T. Schafbauer**, S.-M. Cheng*, Y.-C. Cheng*, D. Vietzke*, M. Eller**, C. Lin**, Q. Ye**, N. Rovedo, S. Biesemans, P. Nguyen, R. Dennard and B. Chen |
| IBM Semiconductor Research and Development Center, *Infineon Technologies and **United Microelectronics, USA |
Wednesday, June 13
20:00-22:00 |
Rump Sessions |
| Organizers |
T. Kunio, NEC
C. Dennison, Ovonyx |
J-R |
Which Features of an IC Technology will Benefit Radio SOC? |
Moderators |
H. Iwai, Tokyo Inst. of Tech.
S. Shichijo, TI
M. Hotta, Hitachi
A. Abidi, UCLA
|
Panelists |
A. Matsuzawa, Matsushita Electric
H. Sato, Mitsubishi Electric
S.-C. Wong, TSMC
F. Behbahani, Valence Semiconductor
E. MacRobbie, Conexant Systems
R. Rofougaran, Broadcom
|
|
Integration of radio and digital functions on a single chip beyond todays cellular prototypes will enable a new generation of radio devices with potentially very large markets. To meet the targets of low cost and low power, what are reasonable levels of integration? What are the most important IC technology attributes to enable this: transistor fT, density, on-chip passives, substrate isolation, etc.? Which one mainstream technology best embodies these features?
|
R-1 |
High-K Gate Dielectrics: Is It Necessary ? If So, When, What, How ? |
Moderators |
M. Niwa, Matsushita Electric
J.C. Lee, TI
|
Panelists |
H.-K. Kang, Samsung Electronics
Y. Tsunashima, Toshiba
D. Buchanan, IBM
R. Chau, Intel
J. Hauser, North Carolina State Univ.
M. Heyns, IMEC
D.-L. Kwong, Univ. of Texas
L. Manchanda, Agere Systems
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High-K materials have attracted a great deal of attention recently for gate dielectric applications. However, there are still many unanswered questions. In this session, we will address some of the key issues involving integration of high-K thin films for gate dielectric applications.
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Recently, there have been several exciting reports on high-quality ultra-thin SiO2 (e.g. 0.8 nm). Will high-K materials ever be used? |
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If so, at what technology node can we expect high-K films to be used for gate dielectric applications? |
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What are the most important criteria for high-K gate dielectrics (e.g. leakage current, reliability, uniformity, process compatibility)? |
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What are the most promising material candidates (e.g. Al2O3, HfO2, ZrO2, silicates, La2O3, Ta2O5, Pr2O3, etc.)? |
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What are the most promising deposition methods for high-K thin films (e.g. PLD, CVD, ALD, JVD, and what precursors)? |
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What are the important integration issues to be considered in order to incorporate high-k gate dielectrics in CMOS technology (e.g. gate electrode, sidewall spacer materials, cross-contamination, source/drain engineering, dopant diffusion)? |
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Currently there are only a few, if any, 8" pilot lines available for qualifying high-K materials in advanced device structures. What approach should we use in order to bring these high-K films to manufacturing ? (e.g. consortium ?) |
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R-2 |
Extending Copper/low k Interconnects to 100 nm and Beyond: How "Low" Can We Go? Are There Any Alternative Approaches? |
Moderators |
Y. Hayashi, NEC
B. Havemann, Novellus Systems
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Panelists |
I. Doi, Asahi Kasei
M. Yamada, Fujitsu
C.-H.(D.) Yu, TSMC
H.-J. Barth, Infineon
M. Mills, Dow Chemical
M. Thomas, Honeywell
J. Wetzel, Sematech/Motorola
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For the past decade, introduction of new interconnect materials and/or processes at each successive generation has become more the norm than the exception, and this trend is expected to continue in the race for improved performance, reliability and density. Near term needs include lower permittivity (low k) dielectrics for conductor insulators and copper diffusion barriers, higher permittivity materials for decoupling capacitors and new metal barriers/processes for copper. Integration of these new materials presents a formidable challenge. Integration risks are especially severe at the 100 nm node and beyond, where the ITRS forecasts a performance-driven need for dielectric materials with k values less than 2.0, and thermal, mechanical and electrical properties may be incompatible with current process and packaging techniques. Additional issues include the scalability of copper itself, since both resistivity and reliability are expected to degrade as feature size decreases. This panel will address the risk versus reward of extending Cu/low k technology to address the perceived "performance crisis" and explore alternative approaches to high performance wiring solutions.
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R-3 |
Technology Challenges and Solutions for Scaling Flash Memory-What Do the Next Ten Years Promise? |
Moderators |
R. Shirota, Toshiba
K. Parat, Intel
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Panelists |
T. Kobayasi, Hitachi
S. Pan, Macronix
K. Park, Samsung Electronics
R. Bez, STMicroelectronics
S. Haddad, AMD
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Since the conception of Flash memory device in 1984, the memory cell has scaled by over 200X in size. During this period a number of new technology scaling elements and new process architectures have been introduced as well as several enhancements have been made to the operation of the cell in order to achieve the scaling. Additionally, a number of new cell structures and cell architectures have been proposed as well as introduced into production with promises for better scalability as well as smaller cell. A breakthrough approach of storing four or more levels in a Flash memory cell, which effectively allows scaling of the bit size for a given cell size, has been used as well.
The question today facing the Flash community at large is-How far will this scaling trend continue. How small can the flash cell size become? How many numbers of bits per cell can be achieved ? What are the technology challenges, roadblocks and performance bottlenecks for continued scaling of flash? What is the fundamental limit for scaling of the cell size. What is the fundamental limit for multi-bit storage? And finally, what would the solution be to these challenges and limitations?
This panel discussion will attempt to answer some of these questions. The panel comprises leading technologists representing the various Flash Memory companies as well as the diverse types of Flash memories such as NOR, NAND, DINOR, AND, etc. Discussion amongst the panelists as well as interaction with the members of the audience should help highlight the various issues and concerns as well as address some of these, paving the way for Flash scaling roadmap for the next several generations.
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Session 9A |
Nonvolatile Memory Technology [Shunju I] |
| Chairpersons |
T. Nakamura, Rohm
R. Bez, STMicroelectronics |
8:30 |
9A-1 |
Highly Scalable sub-10F2 1T1C COB Cell for high density FRAM |
| Abstract |
S.Y. Lee, H.H. Kim, D.J. Jung, Y.J. Song, N.W. Jang, M.K. Choi, B.K. Jeon, Y.T. Lee, K.M. Lee, S.H. Joo, S.O. Park and K. Kim |
| Samsung Electronics Co. Ltd., Korea |
8:55 |
9A-2 |
A Fully Planalized 8M bit Ferroelectric RAM with 'Chain' Cell Structure |
| Abstract |
T. Ozaki, J. Iba, Y. Yamada, H. Kanaya, T. Morimoto, O. Hidaka, A. Taniguchi, Y. Kumura, K. Yamakawa, Y. Oowaki and I. Kunishima |
| Toshiba Corporation, Japan |
9:20 |
9A-3 |
A Novel Analysis Method of Threshold Voltage Shift due to Detrap in a Multi-level Flash Memory |
| Abstract |
R. Yamada, T. Sekiguchi, Y. Okuyama, J. Yugami and H. Kume |
| Hitachi, Ltd., Japan |
Session 9B |
CMOS Reliability [Shunju II] |
| Chairpersons |
K. Sakamoto, Electrotechnical Lab.
S. Venkatesan, Motorola |
8:30 |
9B-1 |
New Considerations for Highly Reliable PMOSFETs in 100 nm Generation and Beyond |
| Abstract |
E. Morifuji, T. Kumamori, M. Muta, K. Suzuki, I. De*, A. Shibkov*, S. Saxena*, T. Enda, N. Aoki, W. Asano, H. Otani, M. Nishigori, K. Miyamoto, F. Matsuoka, T. Noguchi and M. Kakumu |
| Toshiba Corporation, Japan and *PDF solutions, Inc., USA |
8:55 |
9B-2 |
Impact of Low-Standby-Power Device Design on Hot Carrier Reliability |
| Abstract |
E. Murakami, K. Umeda, T. Yamanaka, S. Kimura, H. Aono, K. Makabe*, K. Okuyama, Y. Ohji, Y. Yoshida, M. Minami, K. Kuroda, S. Ikeda and K. Kubota |
| Hitachi, Ltd. and *Hitachi ULSI Systems co., Ltd., Japan |
9:20 |
9B-3 |
Consistent model for short-channel nMOSFET post-hard-breakdown characteristics |
| Abstract |
B. Kaczer, R. Degraeve, A.D. Keersgieter, K.V. de Mieroop, T. Bearda and G. Groeseneken |
| IMEC, Belgium |
Session 10 |
DRAM Technology II [Shunju I] |
| Chairpersons |
S.-I. Lee, Samsung Electronics
S. Crowder, IBM Microelectronics |
10:05 |
10-1 |
Realization of High Performance Dual Gate DRAMs without Boron Penetration by Application of Tetrachlorosilane Silicon Nitride Films |
| Abstract |
M. Tanaka, S. Saida, F. Inoue*, M. Kojima**, T. Nakanishi**, K. Suguro and Y. Tsunashima |
| Toshiba Corporation, *Fujitsu Limited and **Fujitsu Laboratories Ltd., Japan |
10:30 |
10-2 |
Retention Time Improvement by Fast-Pull and Fast-Cool[FPFC] Ingot Growing Combined with Proper Arrangement of Subsequent Thermal Budget for 0.18um DRAM Cell and beyond |
| Abstract |
K. Ilgweon, K. Jaesoon, L. Kyosung, K. Dongchan, S. Jungho, C. Junho, K. Namsung, Y. Heesik, C. Youngil, P. Juseok, K. Hoyup, S. Youngjin, P. Daeyoung and K. Jibum |
| Hyundai Electronics Co.,Ltd, Korea |
10:55 |
10-3 |
DRAM scaling-down to 0.1µm generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug |
| Abstract |
B.-J. Jin, Y.-P. Kim, B.-Y. Nam, H.-J. Kim, Y.-W. Park and J.-T. Moon |
| Samsung Electronics Co., Ltd., Korea |
11:20 |
10-4 |
A New Storage Node Pad Formation Technology-Line Type SAC with Oxide Spacer(LSOS) and Direct Metal Plug(DMP) - for 0.115µm Tech and Beyond |
| Abstract |
K.H. Yoon, S.C. Park, M.S. Lee, M. Huh, Y.H. Bae, S.I. Kim, J.W. Kim and H.K. Yoon |
| Hyundai Electronics Industries Co. Ltd., Korea |
Session 11 |
High-k Gate Dielectrics [Shunju I] |
| Chairpersons |
Y.-J. Mii, TSMC
M. Cao, Pericom Semiconductor |
13:15 |
11-1 |
Dopant Penetration Effects on Polysilicon Gate HfO2 MOSFET's |
| Abstract |
K. Onishi, L. Kang, R. Choi, E. Dharmarajan, S. Gopalan, Y. Jeon, C.S. Kang, B.H. Lee, R. Nieh and J.C. Lee |
| The University of Texas at Austin, USA |
13:40 |
11-2 |
Performance and Reliability of Ultra Thin CVD HfO2 Gate Dielectrics with Dual Poly-Si Gate Electrodes |
| Abstract |
S.J. Lee, H.F. Luan, C.H. Lee, T.S. Jeon, W.P. Bai, Y. Senzaki*, D. Roberts* and D.L. Kwong |
| The University of Texas and *Schumacher, USA |
14:05 |
11-3 |
Ultra-thin ZrO2 (or Silicate) with High Thermal Stability for CMOS Gate Applications |
| Abstract |
Z.J. Luo, T.P. Ma, E. Cartier*, M. Copel*, T. Tamagawa** and B. Halpern** |
| Yale University, *IBM TJ Watson Research Center and **Jet Process Corporation, USA |
14:30 |
11-4 |
MOS Devices with High Quality Ultra Thin CVD ZrO2 Gate Dielectrics and Self-Aligned TaN and TaN/Poly-Si Gate Electrodes |
| Abstract |
C.H. Lee, Y.H. Kim, H.F. Luan, S.J. Lee, T.S. Jeon, W.P. Bai and D.L. Kwong |
| The University of Texas, USA |
Session 12 |
Multilevel Interconnects [Shunju I] |
| Chairpersons |
S. Onishi, Sharp
B. Havemann, TI/SEMATECH |
15:15 |
12-1 |
Optimizaion of Annealing Conditions for Dual Damascene Cu Microstructures and Via Chain Yields |
| Abstract |
Q.-T. Jiang, A. Frank, R.H. Havemann, V. Parihar* and M. Nowell** |
| International Sematech, *Mattson Technology and **TSL Inc., USA |
15:40 |
12-2 |
Impact of Vias on the Thermal Effect of Deep Sub-Micron Cu/low-k Interconnects |
| Abstract |
T.-Y. Chiang and K.C. Saraswat |
| Stanford University, USA |
16:05 |
12-3 |
Scaling Scenario of Multi-level Interconnects for Future CMOS LSI |
| Abstract |
H. Yoshimura, Y. Asahi and F. Matsuoka |
| Toshiba Corporation, Semiconductor Company, Japan |
16:30 |
12-4 |
Non-Uniform Chip-Temperature Dependent Signal Integrity |
| Abstract |
A.H. Ajami, K. Banerjee* and M. Pedram |
| University of Southern California and *Stanford University, USA |
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