Welcome to the 2003 Symposium on VLSI Circuits
You are cordially invited to attend the 2003 Symposium on VLSI Circuits, to be held on June 12-14th 2003, at the Rhiga Royal Hotel Kyoto in Kyoto, Japan. Following the tradition of the last several years, the Symposium on VLSI Circuits will follow the Symposium on VLSI Technology at the same location.
The Symposium will mark its seventeenth anniversary, establishing as a major international forum for presenting and exchanging ideas on important and exciting new developments in the VLSI circuit design. We have expanded the scope to include new concepts in LSI and physical design tools, in addition to the traditional Analog, Digital, Memory, Signal Processing and Communications circuits. Contributions to the Symposium come from both: industry and academia around the world.
Preceding the Symposium on June 11th, a one-day Short Course on VLSI circuits will be held. This short course will focus on "Low Power Wireless Design". Seven speakers will talk about advanced design techniques for wireless.
This year, the program committee reviewed 206 papers, and selected 77 papers for presentation. These papers disclose new and interesting circuit design concepts for memories, processors, communication circuits, analog, and signal processing. We certainly hope that the technical content of the program will make the Symposium a fruitful and enjoyable event for all the attendees.
We have also invited four distinguished speakers to describe recent advances and new challenges in VLSI; perspective of semiconductor business, nanoelectronic circuits, RF CMOS, and ubiquitous computing.
To complement the formal talks, we have arranged four evening rump sessions on interesting and provocative subjects to give you an opportunity to participate in the discussions with international participants. The rump session topics cover power management, unified custom memory, training analog designers, and reconfigurable processor.
This booklet contains the advance program together with forms for the Symposium registration and hotel reservations. Please try to complete and return these forms as soon as possible. Although the on-site registration will be available at the conference, pre-registration will facilitate Symposium planning.
We look forward to meeting with you at the Symposium in Kyoto.
|
Yoshinobu Nakagome |
Bruce Gieseke |
| Program Chair |
Program Co-Chair |
CONFERENCE SCHEDULE
Tuesday, June 10 |
8:00-17:00 |
Registration |
| Wednesday, June 11 |
7:00 |
Breakfast [Suzaku] |
| 8:00 |
Registration |
| 8:40-12:15 |
Short Course [Suzaku] |
| 13:30-17:05 |
Short Course [Suzaku] |
| 18:00-20:00 |
Reception [Suzaku I] |
| 20:00-22:00 |
Technology and Circuits Joint Rump Session [Suzaku] |
| Thursday, June 12 |
7:00 |
Breakfast [Salon de Charme, Kitayamasugi] |
| 8:00 |
Registration |
8:30-10:15 |
Session 1 |
Welcome and Plenary Session I [Suzaku] |
| 10:35-12:15 |
Session 2 |
Advanced Clock Design [Suzaku] |
| 13:45-15:25 |
Session 3 |
RF Passive Elements [Suzaku I] |
| Session 4 |
Low Power Design [Suzaku II] |
| Session 5 |
High Speed Serial Links I [Suzaku III] |
| 15:45-17:25 |
Session 6 |
Data Converters [Suzaku I] |
| Session 7 |
Memory for SOC [Suzaku II] |
| Session 8 |
High Speed Serial Links II [Suzaku III] |
| 20:00-22:00 |
Rump Sessions [Suzaku I,II,III] |
| Friday, June 13 |
7:00 |
Breakfast [Suzaku] |
| 8:30-10:00 |
Session 9 |
Plenary Session II [Shunju] |
| 10:20-12:00 |
Session 10 |
Wireless Transceivers [Shunju] |
| 13:30-15:10 |
Session 11 |
RF Building Blocks I [Shunju I] |
| Session 12 |
Sensors [Shunju II] |
| Session 13 |
Ferroelectric RAM [Shunju III] |
| 15:30-17:10 |
Session 14 |
Clock/Frequency Synthesis [Shunju I] |
| Session 15 |
Design for Robustness [Shunju II] |
| Session 16 |
Flash and MRAM [Shunju III] |
| 18:00-20:00 |
Dinner [Suzaku] |
| Saturday, June 14 |
7:00 |
Breakfast [Suzaku] |
| 8:30-10:10 |
Session 17 |
RF Building Blocks II [Shunju I] |
| Session 18 |
Digital Building Blocks [Shunju II] |
Session 19 |
SRAMs [Shunju III] |
| 10:30-12:10 |
Session 20 |
Advanced Analog Techniques [Shunju I] |
| Session 21 |
Interconnects and Flexible Processor [Shunju II] |
| Session 22 |
DLLs and DRAM [Shunju III] |
PROGRAM
Wedensday, June 11
20:00-22:00 |
Joint Rump Session with Technology |
J-R |
Judgement Day for Power Management |
| Organizers |
T. Hiramoto, Univ. of Tokyo
T. Kawahara, Hitachi
K. Bernstein, IBM
P. Rickert, Texas Instruments
|
| Moderators |
S. Natarajan, ATMOS/MOSYS
P. Rickert, Texas Instruments
|
Panelists |
H. Ando, Fujitsu
M. Horiguchi, Hitachi
T. Sakurai, Univ. of Tokyo
D. Ditzel, Transmeta
J. Graham HP
D. Sylvester, Univ. Michigan
C. Wann, IBM
|
Dear Circuit, Architecture, and Device/Process Panelist Vice Presidents:
Our audience shareholders will be meeting in a VLSI Symposium panel discussion session this year to decide which of your three teams has made the most important contributions towards resolving the urgent ULSI power consumption crisis, and which of you needs to be replaced. Both dynamic and static power is out of control, and we can no longer accept your promises. Each of you will be given a brief opportunity to defend your discipline's past achievements and to describe your plans for the next technology generation. You then will face your shareholder's questions and complaints. The meeting will conclude with a shareholder decision of who gets the promotion to CTO, who receives more worthless stock options, and who starts a new career in marketing.
|
Session 1 |
Welcome and Plenary Session I [Suzaku] |
| Chairpersons |
Y. Nakagome, Hitachi
B.Gieseke, AMD |
8:30 |
1-1 |
Welcome and Opening Remarks |
| |
M. Yamashina, S. Borkar |
| NEC, Intel |
8:45 |
1-2 |
Semiconductor Industry: The Name of the Game (Invited) |
|
Abstract
|
T. Iizuka |
| THine Electronics, Inc., Japan |
9:30 |
1-3 |
A Top-Down Look at Bottom-up Electronics (Invited) |
|
Abstract
|
M. Lundstrum |
| Purdue Univ., USA |
Session 2 |
Advanced Clock Design [Suzaku] |
| Chairpersons |
H. Kabuo, Matsushita Electric
G. Taylor, Intel |
10:35 |
2-1 |
Clock Generation and Distribution for the Third Generation Itanium® Processor |
|
Abstract
|
S. Tam, U. Desai and R. Limaye |
| Intel Corporation, USA |
11:00 |
2-2 |
A Post-Silicon Clock Timing Adjustment Using Genetic Algorithms |
|
Abstract
|
E. Takahashi, Y. Kasai, M. Murakawa and T. Higuchi |
| AIST, Japan |
11:25 |
2-3 |
Clock Generation and Distribution for Intel Banias Mobile Microprocessor |
|
Abstract
|
E. Fayneh and E. Knoll |
| Intel Corporation, Israel |
11:50 |
2-4 |
A Design for Digital, Dynamic Clock Deskew |
|
Abstract
|
C.E. Dike, N.A. Kurd, P. Patra and J. Barkatullah |
| Intel Corporation, USA |
Session 3 |
RF Passive Elements [Suzaku I] |
| Chairpersons |
M. Nagata, Kobe Univ.
P. Kinget, Columbia Univ. |
13:45 |
3-1 |
21.5dBm Power-Handling 5GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration with Depletion-Layer-Extended Transistors (DETs) |
|
Abstract
|
T. Ohnakado, S. Yamakawa, T. Murakami, A. Furukawa, E. Taniguchi, H. Ueda, N. Suematsu and T. Oomori |
| Mitsubishi Electric Corporation, Japan |
14:10 |
3-2 |
3-Dimensional Vertical Parallel Plate Capacitors in an SOI CMOS Technology for Integrated RF Circuits |
|
Abstract
|
J. Kim, J.-O. Plouchart*, N. Zamdmer, M. Sherony, L.-H. Lu, Y. Tan, M. Yoon, K.A. Jenkins*, M. Kumar, A. Ray and L. Wagner |
| IBM Semiconductor Research and Development Center and *IBM T.J. Watson Research Center, USA |
14:35 |
3-3 |
Very Wide Tuning Range Micro-Electromechanical Capacitors in the MUMPs Process for RF Applications |
|
Abstract
|
T.K.K. Tsang and M.N. El-Gamal |
| McGill University, Canada |
15:00 |
3-4 |
Selective Metal Parallel Shunting Inductor and Its VCO Application |
|
Abstract
|
C.-H. Wu, C.-Y. Kuo and S.-I. Liu |
| National Taiwan University, R. O. C. |
Session 4 |
Low Power Design [Suzaku II] |
| Chairpersons |
K. Seno, Sony
S. Kosonocky, IBM |
13:45 |
4-1 |
A Low-Power Microcontroller Having a 0.5µA Standby Current On-Chip Regulator with Dual-Reference Scheme |
|
Abstract
|
M. Hiraki, K. Fukui and T. Ito |
| Hitachi, Ltd., Japan |
14:10 |
4-2 |
An Integrated Digital Controller for DC-DC Switching Converter with Dual-Band Switching |
|
Abstract
|
M.Y.-K. Chui, W.-H. Ki and C.-Y. Tsui |
| The Hong Kong University of Science and Technology, China |
14:35 |
4-3 |
High-throughput asynchronous datapath with software-controlled voltage scaling |
|
Abstract
|
Y.W. Li, G. Patounakis and K.L. Shepard |
| Columbia University, USA |
15:00 |
4-4 |
Accurate Modeling of Transistor Stacks to Effectively Reduce Total Standby Leakage in Nano-Scale CMOS Circuits |
|
Abstract
|
S. Mukhopadhyay and K. Roy |
| Purdue University, USA |
Session 5 |
High Speed Serial Links I [Suzaku III] |
| Chairpersons |
Y. Ohtomo, NTT Microsystem Integration Labs.
A. Amerasekera, Texas Instruments |
13:45 |
5-1 |
A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface Using Novel Eye-tracking Method |
|
Abstract
|
T. Saito, H. Yamashita, F. Yuki, T. Baba, A. Koyama and M. Sonehara |
| Hitachi, Ltd., Japan |
14:10 |
5-2 |
A 39-to-45-Gbit/s Multi-Data-Rate Clock and Data Recovery Circuit with a Robust Lock Detector |
|
Abstract
|
H. Nosaka, E. Sano*, K. Ishii, M. Ida, K. Kurishima, S. Yamahata and T. Shibata |
| NTT Corporation and *Hokkaido university, Japan |
14:35 |
5-3 |
0.622-8.0Gbps 150mW Serial IO Macrocell with Fully Flexible Preemphasis and Equalization |
|
Abstract
|
R. Farjad-Rad, H.-T. Ng, M.-J.E. Lee, R. Senthinathan, W.J. Dally*, A. Nguyen, R. Rathi, J. Poulton, J. Edmondson, J. Tran and H. Yazdanmehr |
| Velio Communication Inc. and *Stanford University, USA |
Session 6 |
Data Converters [Suzaku I] |
| Chairpersons |
S.-H. Lee, Sogang Univ.
T. Blalock, Univ. of Virginia |
15:45 |
6-1 |
A 0.9V 9mW 1MSPS DIGITALLY CALIBRATED ADC WITH 75dB SFDR |
|
Abstract
|
D.-Y. Chang, G.-C. Ahn and U.-K. Moon |
| Oregon State University, USA |
16:10 |
6-2 |
A 1.8V, 1MS/s, 85dB SNR 2+2 Mash ΣΔ Modulator with ±0.9V Reference Voltage |
|
Abstract
|
K.-S. Lee and F. Maloberti |
| University of Texas at Dallas, USA |
16:35 |
6-3 | A Fourth Order Continuous-Time Complex Sigma-Delta ADC for Low-IF GSM and EDGE Receivers |
|
Abstract
|
F. Esfahani, P. Basedau, R. Ryter and R. Becker |
| Philips Semiconductors AG, Switzerland |
17:00 |
6-4 |
A CMOS Oversampling Bandpass Cascaded D/A Converter with Digital FIR and Current-Mode Semi-Digital Filtering |
|
Abstract
|
D.B. Barkin, A.C.Y. Lin, D.K. Su and B.A. Wooley |
| Stanford University, USA |
Session 7 |
Memory for SOC [Suzaku II] |
| Chairpersons |
C. Kim, Samsung Electronics
S. Natarajan, ATMOS |
15:45 |
7-1 |
A Cost-Efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture |
|
Abstract
|
H. Noda, M. Inoue, H.J. Mattausch*, T. Koide* and K. Arimoto |
| Mitsubishi Electric Corporation and *Hiroshima University, Japan |
16:10 |
7-2 |
Destructive-read Random Access Memory System Buffered with Destructive-read Memory Cache for SoC Applications |
|
Abstract
|
B.L. Ji, S. Munetoh*, C.-L. Hwang, M. Wordeman and T. Kirihata |
| IBM Microelectronics, USA and *IBM Tokyo Research Laboratory, Japan |
16:35 |
7-3 |
The Umbrella Cell: A Logic-Process-Compatible 2T Cell for SOC Applications |
|
Abstract
|
S. Akiyama, N. Oodaira*, T. Ishikawa, D. Hisamoto and T. Watanabe |
| Hitachi, Ltd. and *Hitachi ULSI Systems Co., Ltd., Japan |
17:00 |
7-4 |
A Memory Using One-Transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's |
|
Abstract
|
T. Ohsawa, T. Higashi*, K. Fujita, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, K. Inoh and T. Hamamoto |
| Toshiba Corp. and *Toshiba Microelectronics Corp., Japan |
Session 8 |
High Speed Serial Links II [Suzaku III] |
| Chairpersons |
M. Mizuno, NEC
W. Lee, Texas Instruments |
15:45 |
8-1 |
A 10-mW 3.6-Gbps I/O Transmitter |
|
Abstract
|
H. Hatamkhani, K.-L.J. Wong, R. Drost* and C.-K.K. Yang |
| University of California, Los Angeles and *Sun Microsystems, USA |
16:10 |
8-2 |
A 27-mW 3.6-Gb/s I/O Transceiver |
|
Abstract
|
K.L.J. Wong, M. Mansuri, H. Hatamkhani and C.-K.K. Yang |
| University of California, Los Angeles, USA |
16:35 |
8-3 |
A CMOS 3.5Gbps Continuous-time Adaptive Cable Equalizer with Joint Adaptation Method of Low-Frequency Gain and High-Frequency Boosting |
|
Abstract
|
J.-S. Choi, M.-S. Hwang and D.-K. Jeong |
| Seoul National University, Korea |
17:00 |
8-4 |
3Gbps, 5000ppm Spread Spectrum SerDes PHY with frequency tracking Phase Interpolator for Serial ATA |
|
Abstract
|
M. Aoyama, K. Ogasawara, M. Sugawara*, T. Ishibashi**, T. Ishibashi*, S. Shimoyama*, K. Yamaguchi***, T. Yanagita** and T. Noma |
| NEC Electronics Corporation, Japan, *NEC Electronics America, Inc., USA, **NEC Micro Systems, Ltd. and ***NEC Corporation, Japan |
Thursday, June 12
20:00-22:00 |
Rump Sessions |
Organizers |
Y. Nakagome, Hitachi
S. Kosonocky, IBM |
| R-1 |
What is the Vision of Unified Custom Memory? Main or
Niche?
|
Organizer |
C. Kim, Samsung
|
Organizer/Moderator |
S. Natarajan, ATMOS/MOSYS
|
Panelists |
K. Itoh, Hitachi
J. Kang, Samsung
M. Taguchi, Fujitsu
A. Fazio, Intel
W. Leung, MoSys
P. Rickert, Texas Instruments
|
Memory technologies in the last few decades have been developed as a universal standard to fit various applications, ranging from PC to consumer electronics.
Future emerging memory technologies should provide a total system solution like SOC. The emerging memory trends will try to provide a unified solution targeting optimal process cost, performance and power. This will be made possible by merging various technologies by either integrated process or packaging, and hence will serve as a unified “Custom Memory” i.e., DRAM, SRAM, NVM, and LOGIC combined together to provide a total system solution or lead to the emergence of new technologies i.e. MRAM, FRAM, or PRAM. This panel session will outline the possible market and the value-added application fields and conclude the feasibility of a unified “Custom memory”.
|
R-2 |
Who is Training Analog Designers- Industry or University? |
Organizers |
A. Hyogo, Tokyo Univ. of Science
K. Roy, Purdue Univ.
|
Moderator |
C. Mangelsdorf, Analog Devices
|
Panelists |
M. Hotta, Hitachi
S.-H. Lee, Sogang Univ.
A. Matsuzawa, Matsushita
K. Sekine, Tokyo Univ. of Science
C.-K. Wang, National Taiwan Univ.
A. Abidi, UCLA
K. Suyama, Epoch
G. Uehara, Si Lab
|
Though analog design classes are being taught at the undergraduate level, the number of students working in the area has decreased over time while the need for good analog designers has increased. Most schools are also facing the problem of recruiting faculty in mixed-signal design area, since state of the art analog design are being pursued in the industry. Hence, analog education at the graduate level is suffering in majority of the universities. Probably a joint collaboration between university/industry is required to train analog designers.
R-3 |
What's the Key to Making the Reconfigurable Processor a Success? |
| Organizers |
M. Mizuno, NEC
K. Eckert, AMD
|
| Moderator |
H. Amano, Keio Univ.
|
Panelists |
M. Motomura, NEC
T. Sato, IP Flex
K. Seno, SONY
W. Gass, Texas Instruments
R. Krishnamurthy, Intel
J. Pickett, AMD
|
|
Research and development of the reconfigurable processor (RCP), whose functions can be modified after chip fabrication, has been going on for more than 5 years. RCP has great potential but its application is still unclear. Currently, various architectures focusing on specific domains are individually striving to commercialize their RCPs. What is the key, or what is lacking in successfully commercializing RCP? Is it the tool for applying RCP? Is the architecture still underdeveloped? Is it the performance determined by device/circuit technology? Is the market simply lacking? Or is there no need for dynamic reconfigurability? In this panel we will discuss the scenario for the future success of the RCP by focusing on its potentials and advantages as well as clarify what is lacking in comparison to the other approaches, i.e. configurable processors, chip multi processors.
|
|
Session 9 |
Plenary Session II [Shunju] |
| Chairpersons |
Y. Nakagome, Hitachi
B. Gieseke, AMD |
8:30 |
9-1 |
RF-CMOS Comes of Age (Invited) |
|
Abstract
|
A. Abidi |
| UCLA, USA |
9:15 |
9-2 |
T-Engine: The Open, Real-time Embedded-Systems Platform for Ubiquitous Computing (Invited) |
|
Abstract
|
K. Sakamura and N. Koshizuka |
| Univ. of Tokyo, Japan |
Session 10 |
Wireless Transceivers [Shunju] |
| Chairpersons |
H. Sato, Mitsubishi Electric
P. Kinget, Columbia Univ. |
10:20 |
10-1 |
A 1-V CMOS/SOI Bluetooth RF Transceiver for Compact Mobile Applications |
|
Abstract
|
M. Ugajin, A. Yamagishi, J. Kodate, M. Harada and T. Tsukahara |
| NTT Microsystem Integration Laboratories, Japan |
10:45 |
10-2 |
Gain Calibration and Feedforward Automatic Gain Control for CMOS Radio-Frequency ICs |
|
Abstract
|
W. Hioe, K. Maio, T. Ooshima, Y. Shibahara and T. Doi |
| Hitachi Ltd., Japan |
11:10 |
10-3 |
A CMOS IF Transceiver with 90 dB Linear Control VGA for IMT-2000 Application |
|
Abstract
|
Y.-S. Youn, J.-H. Choi, M.-H. Cho, S.-H. Han and M.-Y. Park |
| Electronics and Telecommunications Research Institute (ETRI), Korea |
11:35 |
10-4 |
A Complete Single-Chip GPS Receiver with 1.6-V 24-mW Radio in 0.18-um CMOS |
|
Abstract
|
T. Kadoyama, N. Suzuki, N. Sasho, H. Iizuka, I. Nagase*, H. Usukubo* and M. Katakura |
| Sony Corporation Semiconductor Network Company and *Sony Semiconductor Kyushu Corporation, Japan |
Session 11 |
RF Building Blocks I [Shunju I] |
| Chairpersons |
T. Kamei, Oki Electric
K. Yang, Univ. of California |
13:30 |
11-1 |
A 0.5-14-GHz 10.6-dB CMOS Cascode Distributed Amplifier |
|
Abstract
|
R.-C. Liu, C.-S. Lin, K.-L. Deng and H. Wang |
| National Taiwan University, Taiwan, R.O.C. |
13:55 |
11-2 |
An optimally transformer coupled, 5GHz Quadrature VCO in a 0.18µm digital CMOS process |
|
Abstract
|
A. Ravi, K. Soumyanath, R.E. Bishop, B.A. Bloechel and L.R. Carley* |
| Intel Corporation and *Carnegie Mellon University, USA |
14:20 |
11-3 |
13.5-mW, 5-GHz WLAN, CMOS Frequency Synthesizer Using a True Single Phase Clock Divider |
|
Abstract
|
S. Pellerano, C. Samori, S. Levantino and A.L. Lacaita |
| Politecnico di Milano, Italy |
14:45 |
11-4 |
A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications |
|
Abstract
|
C.-Y. Wu and C.-Y. Chou |
| National Chiao-Tung University, Taiwan, R.O.C. |
Session 12 |
Sensors [Shunju II] |
| Chairpersons |
M. Ikeda, Univ. of Tokyo
S. Borkar, Intel |
13:30 |
12-1 |
640 × 480 Real-Time Range Finder Using High-Speed Readout Scheme and Column-Parallel Position Detector |
|
Abstract
|
Y. Oike, M. Ikeda and K. Asada |
| University of Tokyo, Japan |
13:55 |
12-2 |
Hotplate-based Conductometric Monolithic CMOS Gas Sensor System |
|
Abstract
|
D. Barrettino, M. Graf, S. Taschini, M. Zimmermann, C. Hagleitner, A. Hierlemann and H. Baltes |
| Swiss Federal Institute of Technology, Switzerland |
14:20 |
12-3 |
A Non-uniformity Correction Scheme Using Multiple Analog Buses for an Uncooled Infrared Sensor |
|
Abstract
|
A. Tanaka, Y. Tanaka, T. Endoh, K. Okuyama and K. Kawano |
| NEC Corporation, Japan |
14:45 |
12-4 |
A New Single Chip Optical CMOS Detector for Next Generation Optical Storage Systems |
|
Abstract
|
I. Hehemann, W. Brockherde, H. Hofmann*, A. Kemna and B.J. Hosticka |
| Fraunhofer Institute of Microelectronic Circuits and Systems and *Thomson, Germany |
Session 13 |
Ferroelectric RAM [Shunju III] |
| Chairpersons |
Y. Takano, Sanyo Electric
H. Pon, Intel |
13:30 |
13-1 |
Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM |
|
Abstract
|
K. Oikawa, D. Takashima, S. Shiratake, K. Hoya and H.O. Joachim* |
| Toshiba Corp. and *Infineon Technologies Japan K.K., Japan |
13:55 |
13-2 |
A Novel Access Scheme suppressing Disturbance for a Cross-point type Ferroelectric Memory |
|
Abstract
|
N. Sakai, Y. Ishizuka, S. Matsushita, Y. Takano, S. Ogasawara, K. Honma, T. Geshi, Y. Inoue and K. Fukase |
| SANYO Electric Co., LTD, Japan |
14:20 |
13-3 |
An Adaptive Reference Generation Scheme for 1T1C FeRAMs |
|
Abstract
|
T. Chandler, A. Sheikholeslami, S. Masui* and M. Oura* |
| University of Toronto, Canada and *Fujitsu Laboratories Limited, Japan |
14:45 |
13-4 |
A 64Mbit Embedded FeRAM Utilizing a 130nm, 5LM Cu/FSG Logic Process |
|
Abstract
|
H. McAdams, R. Acklin, T. Blake, J. Fong, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qui, J. Roscher, A. Seshadri, S. Summerfelt, X. Du*, J. Eliason*, W. Kraus*, R. Lanham**, F. Li**, C. Pietrzyk** and J. Rickes** |
| Texas Instruments, *Ramtron International Corporation and **Agilent Technologies, USA |
Session 14 |
Clock/Frequency Synthesis [Shunju I] |
| Chairpersons |
M. Mizuno, NEC
G. Taylor, Intel |
15:30 |
14-1 |
Low Jitter Butterworth Delay-Locked Loops |
|
Abstract
|
H.-H. Chang, C.-H. Sun and S.-I. Liu |
| National Taiwan University, R. O. C. |
15:55 |
14-2 |
10 GHz, 20mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a .18µm digital CMOS process |
|
Abstract
|
A. Ravi, G. Banerjee, R.E. Bishop, B.A. Bloechel, L.R. Carley and K. Soumyanath |
| Intel Corporation, USA |
16:20 |
14-3 |
A Design of a Compact 2GHz-PLL with a New Adaptive Active Loop Filter Circuit |
|
Abstract
|
M. Toyama, S. Dosho and N. Yanagisawa |
| Matsushita Electric Industrial Co., Ltd., Japan |
16:45 |
14-4 |
A Multiply-by-3 Coupled-Ring Oscillator for Low-Power Frequency Synthesis |
|
Abstract
|
S. Verma, J. Xu and T.H. Lee |
| Stanford University, USA |
Session 15 |
Design for Robustness [Shunju II] |
| Chairpersons |
K. Kobayashi, Kyoto Univ.
K. Bernstein, IBM |
15:30 |
15-1 |
On-Die Droop Detector for Analog Sensing of Power Supply Noise |
|
Abstract
|
A. Muhtaroglu, G. Taylor, T. Rahal-Arabi and K. Callahan |
| Intel Corporation, USA |
15:55 |
15-2 |
Study of Substrate Noise and Techniques for Minimization |
|
Abstract
|
M.S. Peng and H.-S. Lee |
| Massachusetts Institute of Technology, USA |
16:20 |
15-3 |
Enhanced Thermal Management for Future Processors |
|
Abstract
|
M. Ma, S.H. Gunther, B. Greiner, N. Wolff, C. Deutschle and T. Arabi |
| Intel Corporation, USA |
16:45 |
15-4 |
A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits |
|
Abstract
|
C.H. Kim, K. Roy, S. Hsu*, A. Alvandpour*, R.K. Krishnamurthy* and S. Borkar* |
| Purdue University and *Intel Corporation, USA |
Session 16 |
Flash and MRAM [Shunju III] |
| Chairpersons |
M. Hiraki, Hitachi
H. Pon, Intel |
15:30 |
16-1 |
Embedded Twin MONOS Flash Memories with 4ns and 15ns Fast Access Times |
|
Abstract
|
T. Ogura, N. Ogura, M. Kirihara, K.T. Park, Y. Baba, M. Sekine and K. Shimeno |
| Halo LSI, Inc, USA |
15:55 |
16-2 |
A 512kB MONOS type Flash Memory Module Embedded in a Microcontroller |
|
Abstract
|
T. Tanaka, H. Tanikawa, T. Yamaki, Y. Umemoto, A. Kato, Y. Shinagawa and M. Hiraki |
| Hitachi, Ltd., Japan |
16:20 |
16-3 |
An Application Specific Embeddable Flash Memory System for Non-Volatile Storage of Code, Data and Bit-Streams for Embedded EPGA Configurations |
|
Abstract
|
M. Pasotti, G.D. Sandre, D. Iezzi, D. Lena, G. Muzzi, M. Poles and P.L. Rolandi |
| STMicroelectronics, ITALY |
16:45 |
16-4 |
A High-Speed 128Kbit MRAM Core for Future Universal Memory Applications |
|
Abstract
|
A. Bette, J. DeBrosse*, D. Gogl, H. Hoenigschmid, R. Robertazzi**, C. Arndt, D. Braun, D. Casarotto, R. Havreluk**, S. Lammers, W. Obermaier, W. Reohr**, H. Viehmann, W.J. Gallagher** and G. Müller |
| Infineon Technologies, *IBM Microelectronics Division and **IBM Watson Research Center, USA |
Session 17 |
RF Building Blocks II [Shunju I] |
| Chairpersons |
T. Kamei, Oki Electric
K. Yang, Univ. of California |
8:30 |
17-1 |
A Bootstrapping Technique to Improve the Linearity of CMOS Passive Mixers |
|
Abstract
|
F. Tillman and H. Sjöland |
| Lund University, Sweden |
8:55 |
17-2 |
Low 1/f Noise and DC Offset RF Mixer for Direct Conversion Receiver using Parasitic Vertical NPN Bipolar Transistor in Deep N-well CMOS Technology |
|
Abstract
|
I. Nam, Y.J. Kim and K. Lee |
| IKAIST, Korea |
9:20 |
17-3 |
A 1 Volt Switched Transconductor Mixer in 0.18µm CMOS |
|
Abstract
|
E.A.M. Klumperink, S.M. Louwsma, G.J.M. Wienk and B. Nauta |
| University of Twente, The Netherlands |
9:45 |
17-4 |
A 410-mW, 1.22-GHz Downconverter in a Dual-Conversion Tuner IC for OpenCable™ Applications |
|
Abstract
|
R. Montemayor |
| Silicon Wave, Inc., USA |
Session 18 |
Digital Building Blocks [Shunju II] |
| Chairpersons |
Y. Hirose, Fujitsu Labs.
K. Bernstein, IBM |
8:30 |
18-1 |
A 90nm 1GHz 22mW 16x16-bit 2's Complement Multiplier for Wireless Baseband |
|
Abstract
|
B.R. Zeydel, V.G. Oklobdzija, S. Mathew*, R.K. Krishnamurthy* and S. Borkar* |
| University of California and *Intel Corporation, USA |
8:55 |
18-2 |
A 90nm 6.5GHz 256x64b Dual Supply Register File with Split Decoder Scheme |
|
Abstract
|
S. Hsu, B. Chatterjee*, M. Sachdev*, A. Alvandpour, R.K. Krishnamurthy and S. Borkar |
| Intel Corporation, USA and *Univ. of Waterloo, Canada |
9:20 |
18-3 |
3-Transistor Antifuse OTP ROM Array using Standard CMOS Process |
|
Abstract
|
J. Kim and K. Lee |
| KAIST, Republic of Korea. |
9:45 |
18-4 |
A Wide Range 1.0V-3.6V 200Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors |
|
Abstract
|
T. Shimada, H. Notani, Y. Nakase, H. Makino and S. Iwade |
| Mitsubishi Electric Corporation, Japan |
Session 19 |
SRAMs [Shunju III] |
| Chairpersons |
N. Lu, Etron Technology
K. Roy, Purdue Univ. |
8:30 |
19-1 |
A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications |
|
Abstract
|
K. Nii, Y. Tenoh*, T. Yoshizawa, S. Imaoka*, Y. Tsukamoto, Y. Yamagami**, T. Suzuki**, A. Shibayama**, H. Makino and S. Iwade |
| Mitsubishi Electric Corporation, *Mitsubishi Electric Engineering Corporation and **Matsushita Electric Industrial Corporation, Japan |
8:55 |
19-2 |
A Pico-Joule Class, 1 GHz, 32 KByte x 64b DSP SRAM with Self Reverse Bias |
|
Abstract
|
A.J. Bhavnagarwala, S.V. Kosonocky, M. Immediato, D. Knebel and A.-M. Haen |
| IBM T J Watson Research Center, USA |
9:20 |
19-3 |
A Fully Synchronized, Pipelined, and Re-Configurable 50Mb SRAM on 90nm CMOS Technology for Logic Applications |
|
Abstract
|
K. Zhang, U. Bhattacharya, L. Ma, Y. Ng, B. Zheng, M. Bohr and S. Thompson |
| Intel Corporation, USA |
9:45 |
19-4 |
Cosmic-Ray Multi-Error Immunity for SRAM, Based on Analysis of the Parasitic Bipolar Effect |
|
Abstract
|
K. Osada, K. Yamaguchi, Y. Saitoh and T. Kawahara |
| Hitachi, Ltd., Japan |
Session 20 |
Advanced Analog Techniques [Shunju I] |
| Chairpersons |
K. Kotani, Tohoku Univ.
A. Amerasekera, Texas Instruments |
10:30 |
20-1 |
A 40-GHz Frequency Divider in 0.18-µm CMOS Technology |
|
Abstract
|
J. Lee and B. Razavi |
| University of California, Los Angeles, USA |
10:55 |
20-2 |
A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier |
|
Abstract
|
C.-C. Hsu and J.-T. Wu |
| National Chiao-Tung University, Taiwan, R.O.C. |
11:20 |
20-3 |
A Floating-Gate-MOS-Based Low-Power CDMA Matched Filter Employing Capacitance Disconnection Technique |
|
Abstract
|
T. YAMASAKI, T. FUKUDA and T. SHIBATA |
| The University of Tokyo, Japan |
Session 21 |
Interconnects and Flexible Processor [Shunju II] |
| Chairpersons |
M. Matsui, Toshiba
C.-T. Chuang, IBM |
10:30 |
21-1 |
Efficient On-Chip Global Interconnects |
|
Abstract
|
R. Ho, K. Mai and M. Horowitz |
| Stanford University, USA |
10:55 |
21-2 |
Closed-form Analytical Thermal Model for Accurate Temperature Estimation of Multilevel ULSI Interconnects |
|
Abstract
|
T.-Y. Chiang and K.C. Saraswat |
| Stanford University, USA |
11:20 |
21-3 |
The Flexible Processor -Dynamically Reconfigurable Logic Array for Personal-use Emulation System |
|
Abstract
|
T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, K. Leo, S. Kita, K. Kotani and T. Ohmi |
| Tohoku University, Japan |
Session 22 |
DLLs and DRAM [Shunju III] |
| Chairpersons |
H. Ikeda, Elpida Memory
H. McAdams, Texas Instruments |
10:30 |
22-1 |
A Low Cost High Performance Register-Controlled Digital DLL for 1Gbps x32 DDR SDRAM |
|
Abstract
|
J.-T. Kwak, C.-K. Kwon, K.-W. Kim, S.-H. Lee and J.-S. Kih |
| Hynix Semiconductor Inc., Korea |
10:55 |
22-2 |
A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface |
|
Abstract
|
S.J. Kim, S.H. Hong, J.-K. Wee*, J.H. Ahn and J.Y. Chung |
| Hynix Semiconductor and *Hallym University, Korea |
11:20 |
22-3 |
Built-in Duty Cycle Corrector using Coded Phase Blending Scheme for DDR/DDR2 Synchronous DRAM Application |
|
Abstract
|
K. Kim, G. Cho, J.-B. Lee and S.-I. Cho |
| Samsung Electronics, Korea |
11:45 |
22-4 |
Charge-Transferred Presensing and Efficiently Precharged Negative Word-Line Schemes for Low-Voltage DRAMs |
|
Abstract
|
J.-Y. Sim, Y.-G. Gang, K.-N. Lim, J.-Y. Choi, S.-K. Kwak, K.-C. Chun, J.-H. Yoo, D.-I. Seo and S.-I. Cho |
| Samsung Electronics, Korea |
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