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2012 SYMPOSIUM ON VLSI CIRCUITS

Welcome to the 2012 Symposium on VLSI Circuits

PDFPDF of Advance Program (as of May 21)

You are cordially invited to attend the 2012 Symposium on VLSI Circuits, to be held on June 13-15, 2012, at the Hilton Hawaiian Village in Honolulu, Hawaii. Following our rich tradition, the Symposium on VLSI Circuits will follow the Symposium on VLSI Technology at the same location.

Once again, the Circuits Symposium will overlap the Technology Symposium for two full days, and allow participants to freely choose to attend papers from either Symposium. This provides a unique opportunity to learn about the latest advances in both VLSI Circuits and Technology. In addition, for the first time, the Symposia offer 8 Technology/Circuits Joint Focus Sessions on the two overlap days. Papers in these sessions cover topics of interest to both the Technology and Circuits communities, and facilitate highly synergistic interactions among them.

The Symposium on VLSI Circuits has established itself as a premier international forum for presenting and exchanging important ideas and major new developments in VLSI circuit design. The scope of the conference includes new concepts in Digital Circuits, Memory and Analog Circuits for Computing, Memory and Communications in Scaled CMOS and Emerging Technologies. Specifically, the Symposium covers advances in low power and high performance circuit designs in scaled CMOS processes for processors and SoC, SRAM, DRAM, Flash and emerging non-volatile memory, power management, DC-DC converters, data converters, clocking, 3D-stacked designs, wireless and wireline communication circuits. Contributions to the Symposium come from both industry and academia, from around the world.

On June 12th, the day before the Circuits Symposium, two all-day Short Courses are offered by distinguished speakers from industry and academia. For one registration fee, participants can attend either of the courses in parallel and switch freely between them. A roundtable discussion will follow to foster interactions and discussions with the speakers. The first course, focusing on challenges related to logic, memory and analog circuit design, is titled “Designing in Advanced CMOS Technologies.” The other course focuses on the power efficiency challenges of mobile platforms and is titled “Ultra Low Power SoC Design for Future Mobile Systems.”

This year, the technical program committee reviewed 386 papers, selecting 97 outstanding papers for presentation at the Circuits Symposium. These papers disclose new and interesting circuits and designs for memory, processor, communication, analog, data conversion, signal processing, power management, medical and automotive electronics. They represent the leading edge of VLSI circuit design.

We have invited two distinguished industry leaders to describe recent advances and new challenges related to VLSI circuits, technology and applications: “The Evolution of Next Generation Data Center Networks for High Capacity Computing” by Nicholas Ilyadis, Vice President & Chief Technology Officer of the Infrastructure and Networking Group at Broadcom, and “Technology Innovations for Smart Cities” by Akira Maeda, Chief Technology Officer of the Infrastructure Systems Company at Hitachi.

To complement the formal talks, we have arranged three evening rump sessions on interesting and provocative topics to give you an opportunity to participate in the discussions and mix with the industry and academic experts offering their viewpoints on important topics. The rump sessions explore “Scaling Challenges Beyond 1xnm DRAM and NAND Flash”, “Is VLSI Innovation Dead?”, “Will the Future Have More Analog or Digital Processing?”.

We have been organizing a luncheon talk for attendees of Circuits and Technology Symposia to enjoy informative and entertaining speeches on interesting topics in a relaxed atmosphere with excellent food. This year, it will feature the talk “Nano Satellites, CubeSats, and the Next Space Generation” by Prof. James Cutler from University of Michigan.

The rich technical content of the program will undoubtedly interest you, and we certainly hope that the Symposium will be a fruitful and enjoyable experience.

We look forward to meeting with you at the Symposium in Honolulu.



Makoto Nagata

Vivek De
Program Chair Program Co-Chair




CONFERENCE SCHEDULE


Monday 6/11

7:30a-5:00p

Registration
Tuesday, 6/12
7:30a-5:00p Registration
8:30a-5:30p Short Course 1    Short Course 2
6:30p-7:30p Joint Technology / Circuits Reception
8:00p-10:00p Technology and Circuits Joint Rump Session
Wednesday,
6/13
7:30a-5:00p Registration
8:05a-10:05p Session 1 Welcome, Awards and Plenary Session
10:25a-12:05p Session 2 Phase Locked Loops and Oscillators
T-Session 10 Technology/Circuits Joint Focus Session - Memory
Session 3 Analog Devices
1:30p-3:10p Session 4 A/D Converters
T-Session 12 Technology/Circuits Joint Focus Session - 3D-System Integration
Session 5 Ultra Low Power Radios
3:25p-5:30p Session 6 Technology/Circuits Joint Focus Session - Emerging Nonvolatile Memory
Session 7 High Data Rate Wireless and Imaging
7:00p- 9:00p Joint Technology / Circuits Banquet
Thursday, 6/14 8:00a-5:00p Registration
8:05a-9:45a Session 8 Technology/Circuit Joint Focus Session - Advanced SRAM
Session 9 Medical Electronics
10:00a-12:05p Session 10 Wireless Connectivity and Software Defined Radios
T-Session 17 Technology/Circuits Joint Focus Session - Design in Scaled Technologies
Session 11 Successive Approximation A/D Converters
12:05p-1:15p Technology and Circuits Joint Luncheon Talk
1:30p-3:10p Session 12 Technology/Circuit Joint Focus Session - Design Enablement in Scaled CMOS
Session 13 High Performance Transceivers
3:25p-5:30p Session 14 Technology/Circuit Joint Focus Session - Embedded Memory
Session 15 Analog Sensor Interfaces
8:00p-10:00p Circuits Rump Session
Friday, 6/ 15 8:00a-3:00p Registration
8:05a-9:45a
Session 16 Special Focus Session - Flash Memory
Session 17 Low Power Receivers and Jitter Reduction
10:00a-12:05p Session 18 SoC and Signal Processors
Session 19 Delta-Sigma Converters
1:45p-3:25p Session 20 Clock and Interconnect
Session 21 DC-DC Converters
3:25p-5:30p Session 22 Digital Timing Generations Circuits
Session 23 Power Management Circuits





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