Welcome to the 2003 Symposium on VLSI Technology On behalf of the organizing Committees, you are cordially invited to attend the 2003 Symposium on VLSI Technology to be held from June 10-12 in Kyoto, Japan. This symposium has established itself as one of the most important international forums for presenting the latest research and developments in the area of VLSI and ULSI technologies and their applications. We selected 84 very high quality papers from 199 contributed papers submitted from all over the world, and organized them into 21 sessions. We are also delighted to have two distinguished Invited Speakers for the Plenary Session. Prof. Y. Nishimura, University of Tokyo, will speak on “Proposal of the System Platform - A Semiconductor Business Model in the Age of Digital Consumer Products”, and Dr. Tak H. Ning of IBM will speak on “Silicon Technology-Emerging Trends from a System Application Perspective”. Four Rump Sessions are planned for the evening as a means to facilitate informal discussions among the researchers. Three of the four are regular sessions, and will cover specific technology related topics of timely interest; 1) High-k Gate Dielectrics: Are They Put in Practical Use at Suitable Time? 2) Interconnecting Interconnect Technology and Packaging 3) Embedded Non-Volatile Memories - What eNVM Technologies Will Dominate the SoC Memory Markets in the Next 10 Years? The other one is a Joint Session with the Symposium on VLSI Circuits which will address “Judgement Day for Power Management”. A one-day Short Course, scheduled for Monday June 9, will cover “SOC Technologies for Future Technology Generations”. This should be an excellent opportunity for experienced as well as new engineers to broaden their technical base. The symposium registration fee covers all of the sessions including the Rump Sessions. Coffee breaks and the dinner are also included. Registration for the Short Course is extra. The detailed registration fees and hotel reservation schedules are included in the Advance Program. As in past years, we expect a strong participation from leaders of VLSI industry and academic researchers. We look forward to an exciting Symposium in Kyoto. Please join us. Kenji Maeguchi Bob Havemann Program Chair Program Co-Chair CONFERENCE SCHEDULE Sunday, June 8 8:00-17:00 Registration Monday, June 9 7:00 Breakfast [Suzaku] 8:00 Registration 8:55-12:15 Short Course [Shunju] 13:45-17:00 Short Course [Shunju] 18:00-20:00 Reception [Suzaku] Tuesday, June 10 7:00 Breakfast [Suzaku] 8:00 Registration 8:20-9:55 Session 1 Welcome and Plenary Session [Shunju] 10:10-11:50 Session 2 Highlights [Shunju] 13:30-15:35 Session 3A High-K Gate Dielectric I [Shunju] Session 3B Non-Volatile Memory I [Suzaku] 15:55-17:10 Session 4A RF/Analog Devices [Shunju] Session 4B Lithography [Suzaku] 18:30-20:30 Dinner [Shunju] Wednesday, June 11 7:00 Breakfast [Suzaku, Salon de Charme] 8:30-10:10 Session 5A High Performance Devices [Shunju I] Session 5B DRAM [Shunju II] 10:30-12:10 Session 6A High Performance Technology I [Shunju I] Session 6B DRAM/MIM Capacitor [Shunju II] 13:30-15:10 Session 7A High Performance Technology II [Shunju I] Session 7B Nov-Volatile Memory II [Shunju II] 15:30-17:10 Session 8A Strained Silicon MOSFET [Shunju I] Session 8B Multilevel Interconnects I [Shunju II] 20:00-22:00 Rump Sessions [Suzaku, Momiji, Matsu, Sakura] Thursday, June 12 7:00 Breakfast [Salon de Charme, Kitayamasugi] 8:30-10:10 Session 9A Advanced CMOS I [Shunju I] Session 9B Multilevel Interconnects II [Shunju II] 10:30-12:10 Session 10A Advanced CMOS II [Shunju I] Session 10B Gate Dielectric Technology [Shunju II] 13:30-14:45 Session 11A Damascene and Metal Gate Technology [Shunju I] Session 11B Process Technology [Shunju II] 15:05-17:10 Session 12A High-K Gate Dielectric II [Shunju I] Session 12B Advanced Memory [Shunju II] PROGRAM Tuesday, June 10 Session 1 Welcome and Plenary Session [Shunju] Chairpersons K. Maeguchi, Toshiba B. Havemann, Novellus Systems 8:20 1-1 Welcome and Opening Remarks    S. Kawamura, Y. Taur Advanced Semiconductor Res. Center, Univ. of California 8:35 1-2 Proposal of the System Platform-A Semiconductor Business Model in the Age of Digital Consumer Products (Invited) Abstract Y. Nishimura Univ. of Tokyo, Japan 9:15 1-3 Silicon Technology-Emerging Trends from a System Application Perspective (Invited)    T.H. Ning IBM Thomas J. Watson Research Center, USA back to conference schedule (Break 9:55-10:10) Tuesday, June 10 Session 2 Highlights [Shunju] Chairpersons S.S. Chung, , National Chiao Tung Univ. S. Crowder, IBM Microelectronics 10:10 2-1 Fermi Level Pinning at the PolySi/Metal OxideInterface Abstract C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde,D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai,L. Hebert, H. Tseng, B. White and P. Tobin Motorola, USA 10:35 2-2 The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88nm feature size and beyond Abstract J.Y. Kim, C.S. Lee, S.E. Kim, I.B. Chung, Y.M. Choi, B.J. Park, J.W. Lee, D.I. Kim, Y.S. Hwang,D.S. Hwang, H.K. Hwang, J.M. Park, D.H. Kim, N.J. Kang, M.H. Cho, M.Y. Jeong, H.J. Kim, J.N. Han, S.Y. Kim, B.Y. Nam, H.S. Park, S.H. Chung, J.H. Lee, J.S. Park, H.S. Kim, Y.J. Park and K. Kim Samsung Electronics Co., Korea 11:00 2-3 Highly Stable 65nm Node (CMOS5) 0.56um2 SRAM Cell Design for Very Low Operation Voltage Abstract M. Kanda, E. Morifuji, M. Nishigoori, Y. Fujimoto, M. Uematsu*, K. Takahashi, H. Tsuno, K. Okano, S. Matsuda, H. Oyamatsu, H. Takahashi*, N. Nagashima*, S. Yamada, T. Noguchi, Y. Okamoto* and M. Kakumu TOSHIBA Corporation and *SONY Corporation, Japan 11:25 2-4 A 0.18µm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications Abstract A.R. Sitaram, D.W. Abraham*, C. Alof, D. Braun, S. Brown*, G. Costrini**, F. Findeis, M. Gaidis**, E. Galligan*, W. Glashauser, A. Gupta, H. Hoenigschmid, J. Hummel**, S. Kanakasabapathy*, I. Kasko, W. Kim, U. Klostermann, G.Y. Lee, R. Leuschner, K.-S. Low, Y. Lu*, J. Nützel*, E. O’Sullivan*, C. Park, W. Raberg, R. Robertazzi*, C. Sarma, J. Schmid, P.L. Trouilloud*, D. Worledge*, G. Wright*, W.J. Gallagher* and G. Müller Infineon Technologies, *IBM Watson Research Center and **IBM Microelectronics Division, USA back to conference schedule (Lunch 11:50-13:30) Tuesday, June 10 Session 3A High-K Gate Dielectric I [Shunju] Chairpersons T. Hiramoto, Univ. of Tokyo J. Woo, Univ. of California 13:30 3A-1 Fabrication of HfSiON Gate Dielectrics by Plasma Oxidation and Nitridation, Optimized for 65nm node Low Power CMOS Applications Abstract S. Inumiya, K. Sekine, S. Niwa, A. Kaneko, M. Sato, T. Watanabe, H. Fukui, Y. Kamata, M. Koyama, A. Nishiyama, M. Takayanagi, K. Eguchi and Y. Tsunashima Toshiba Corporation, Japan 13:55 3A-2 Design Guideline of HfSiON Gate Dielectrics for 65 nm CMOS Generation Abstract T. Watanabe, M. Takayanagi, R. Iijima*, K. Ishimaru, H. Ishiuchi and Y. Tsunashima Toshiba Corporation Semiconductor Company and *Toshiba Corporation, Japan 14:20 3A-3 Comparison of sub 1 nm TiN/HfO2 with Poly-Si/HfO2 gate stacks using scaled chemical oxide interfaces Abstract W. Tsai, L. Ragnarsson*, P.J. Chen**, B. Onsia*, R.J. Carter*, E. Cartier***, E. Young****, M. Green*****, M. Caymax*, S.D. Gendt* and M. Heyns* Intel Corp., *IMEC, **Texas Instruments, ***IBM, ****Philips and *****Agere Systems, Belgium 14:45 3A-4 Novel Plasma Enhanced Atomic Layer Deposition Technology for High-k Capacitor with EOT of 8Å on Conventional Metal Electrode Abstract S.-J. Won, Y.-K. Jeong, D.-J. Kwon, M.-H. Park, H.-K. Kang, K.-P. Suh, H.-K. Kim, J.-H. Ka, K.-Y. Yun, D.-H. Lee, D.-Y. Kim*, Y.-M. Yoo* and C.-S. Lee* Samsung Electronics Co.,Ltd. and *Genitech Co., Ltd., Korea 15:10 3A-5 Design and Proof of High Quality HfAlOx Film Formation for MOSCAPs and nMOSFETs through Layer-by-Layer Deposition and Annealing Process Abstract T. Nabatame, K. Iwamoto, H. Ota*, K. Tominaga, H. Hisamatsu, T. Yasuda*, K. Yamamoto, W. Mizubayashi*, Y. Morita*, N. Yasuda, M. Ohno, T. Horikawa and A. Toriumi* MIRAI-ASET and *MIRAI-ASRC, Japan back to conference schedule (Break 15:35-15:55) Tuesday, June 10 Session 3B Non-Volatile Memory I [Suzaku] Chairpersons T. Kobayashi, Sony R. Bez, STMicroelectronics 13:30 3B-1 Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer Abstract T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi and H. Tanaka FUJITSU LABORATORIES LTD., Japan 13:55 3B-2 3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications Abstract A.J. Walker, S. Nallamothu, E.-H. Chen, M. Mahajani, S.B. Herner, M. Clark*, J.M. Cleeves, S.V. Dunton, V.L. Eckert, J. Gu, S. Hu, J. Knall, M. Konevecki, C. Petti, S. Radigan, U. Raghuram, J. Vienna, M.A. Vyvoda Matrix Semiconductor Inc. and *University of Florida, USA 14:20 3B-3 Highly Manufacturable SONOS Non-Volatile Memory for the Embedded SoC Solution Abstract J.-H. Kim, I.W. Cho, G.J. Bae, S.S. Kim, K.C. Kim, S.H. Kim, K.W. Koh, N.I. Lee, H.-K. Knag, K.-P. Suh, S.T. Kang, M.K. Seo, S.H. Lee, M.C. Kim and I.S. Park Samsung Electronics Co., Ltd., Korea 14:45 3B-4 Theoretical and Experimental Investigation of Si Nanocrystal Memory Device with HfO2 High-k Tunneling Dielectric Abstract J.J. Lee, X. Wang, W. Bai, N. Lu, J. Liu and D.L. Kwong The University of Texas, USA 15:10 3B-5 Silicon Nitride Trap Memory with Double Tunnel Junction Abstract R. Ohba, N. Sugiyama, J. Koga and S. Fujita Toshiba Corporation, Japan back to conference schedule (Break 15:35-15:55) Tuesday, June 10 Session 4A RF/Analog Devices [Shunju] Chairpersons T. Dan, Sanyo Electric B. Zhao, Skyworks Solutions 15:55 4A-1 The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11 µm CMOS Abstract T. Ohguro, Y. Okayama, K. Matsuzawa, K. Matsunaga, N. Aoki, K. Kojima, H.S. Momose and K. Ishimaru Toshiba Corporation, Japan 16:20 4A-2 Low-K/Cu CMOS Logic Based SoC Technology for 10Gb Transceiver with 115GHzfT, 80GHz fMAX RF CMOS, High-Q MiM Capacitor and Spiral Cu Inductor Abstract J.C. Guo, W.Y. Lien, M.C. Hung, C.C. Liu, C.W. Chen, C.M. Wu, Y.C. Sun and P. Yang Taiwan Semiconductor Manufacturing Company, Taiwan, R.O.C. 16:45 4A-3 Integration of 10Gb/sec Silicon Lateral Trench Photodetector with High-Performance CMOS Abstract M. Yang, J.D. Schaub, D.L. Rogers, J.A. Griesemer, D.C. Boyd, B. Zhang, F. Rodier*, P.L. Flaitz, J.S. McMurray, K.K. Chan, B. Kim, M.J. Breitwisch, J.P. Walko, D. Pendleton, K.L. Holloway, M.B. Ritter, J.A. Kash and M. Ieong IBM Semiconductor Research and Development Center (SRDC), USA and *Altis Semiconductors, France back to conference schedule (Dinner 18:30-20:30) Tuesday, June 10 Session 4B Lithography [Suzaku] Chairpersons K. Shibahara, Hiroshima Univ. P. Zeitzoff, International SEMATECH 15:55 4B-1 Local Flare Effects and Correction in ArF Lithography Abstract T. Yao, M. Osawa, T. Minami, N. Yamamoto, H. Aoyama, G. Okuda, T. Sawano, I. Kamatsuki, F. Sugimoto, H. Futatsuya, K. Kobayashi, K. Ogino, H. Hoshino, Y. Machida, H. Arimoto and S. Asai Fujitsu Limited, Japan 16:20 4B-2 ArF Lithography Technologies for 65nm-node CMOS (CMOS5) with 30nm Logic Gate and High Density Embedded Memories Abstract K. Hashimoto, F. Uesawa*, K. Takahata, K. Kikuchi*, H. Kanai, H. Shimizu*, E. Shiobara, K. Takeuchi*, A. Endo, H. Harakawa and S. Mimotogi Toshiba Corporation and *Sony Corporation, Japan 16:45 4B-3 Cost-effective Production using Electron Projection Lithography for 65-nm Node SoC and Beyond Abstract H. Yamashita, K. Nakajima*, I Amemiya**, S. Kawata***, S. Nakatsuka**, I. Kimura**, T. Fujiwara***, Y. Yamada*, K. Fujii* and M. Yamabe Selete, *NEC Electronics Corp., **HOYA Corp. and ***Nikon Corp., Japan back to conference schedule (Dinner 18:30-20:30) Wednesday, June 11 Session 5A High Performance Devices [Shunju I] Chairpersons C.H. Diaz, TSMC S. Deleonibus, LETI 8:30 5A-1 High Performance 35 nm Gate CMOSFETs with Vertical Scaling and Total Stress Control for 65 nm Technology Abstract K. Goto, Y. Tagawa, H. Ohta, H. Morioka, S. Pidin, Y. Momiyama, K. Okabe*, H. Kokura, S. Inagaki, Y. Kikuchi**, M. Kase, K. Hashimoto, M. Kojima and T. Sugii Fujitsu limited., *Fujitsu VLSI Process Technology Laboratory Ltd. and **Fujitsu Laboratories LTd, Japan 8:55 5A-2 A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics Abstract T. Ernst, F. Ducroquet*, J.-M. Hartmann, O. Weber, V. Loup, R. Truche, A.M. Papon, P. Holliger, B. Prévitali, A. Toffoli, J.L.D. Maria and S. Deleonibus CEA/DRT-LETI and *LPM, France 9:20 5A-3 Improvement of Threshold Voltage Roll-off by Ultra-shallow Junction Formed by Flash Lamp Annealing. Abstract T. Ito, K. Suguro, T. Itani, K. Nishinohara, K. Matsuo and T. Saito Toshiba Corporation, Japan 9:45 5A-4 Ultimate Solution for Low Thermal Budget Gate Spacer and Etch Stopper to Retard Short Channel Effect in Sub-90nm Devices Abstract J.-H. Yang, J.-E. Park, J.-W. Lee, K.-S. Chu, J.-H. Ku, M.-H. Park, N.-I. Lee, H.-S. Kang, M.-H. Oh, J.-H. Lee, H.-K. Kang and K.-P. Suh Samsung Electronics Co., Ltd., Korea back to conference schedule (Break 10:10-10:30) Wednesday, June 11 Session 5B DRAM [Shunju II] Chairpersons H. Matsuoka, Hitachi L. Tran, Micron Technology 8:30 5B-1 Robust Memory Cell Capacitor using Multi-Stack Storage Node for High Performance in 90nm Technology and Beyond Abstract J. Lee, Y. Ahn, Y. Park, M. Kim, D. Lee, K. Lee, C. Cho, T. Chung and K. Kim Samsung Electronics Co., Korea 8:55 5B-2 Technologies for Scaling Vertical Transistor DRAM Cells to 70nm Abstract R. Divakaruni, C. Radens, M. Belyansky, M. Chudzik, D.-G. Park, S. Saroop, D. Chidambarrao, M. Weybright, H. Akatsu, L. Economikos, K. Settlemyer, J. Strane, D. Dobuzinsky, N. Edleman, G. Feng, Y. Li, R. Jammy, E. Crabbé and G. Bronner IBM Microelectronics, USA 9:20 5B-3 Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM Abstract R. Katsumata, N. Tsuda, J. Idebuchi, M. Kondo, N. Aoki, S. Ito, K. Yahashi, T. Satonaka, M. Morikado, M. Kito, M. Kido, T. Tanaka, H. Aochi and T. Hamamoto TOSHIBA Corporation, Japan 9:45 5B-4 FBC (Floating Body Cell) for Embedded DRAM on SOI Abstract K. Inoh, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, T. Ohsawa, T. Higashi*, K. Fujita, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Hamamoto and H. Ishiuchi Toshiba Corp. and *Toshiba Microelectronics Corp., Japan back to conference schedule (Break 10:10-10:30) Wednesday, June 11 Session 6A High Performance Technology I [Shunju I] Chairpersons J.H. Lee, Hynix Semiconductor S. Sharifzadeh, Cypress Semiconductor 10:30 6A-1 A Functional 0.69µm2 Embedded 6T-SRAM bit cell for 65nm CMOS platform Abstract F. Arnaud, F. Boeuf, F. Salvetti*, D. Lenoble, F. Wacquant, C. Regnier, P. Morin, N. Emonet, E. Denis, J.C. Oberlin, D. Ceccarelli, P. Vannier, G. Imbert, A. Sicard, C. Perrot, O. Belmont, I. Guilmeau**, P.O. Sassoulas, S. Delmedico, R. Palla, F. Leverd, A. Beverina, V. DeJonghe*, M. Broekaart*, L. Pain**, J. Todeschini*, M. Charpin**, Y. Laplanche, D. Neira, V. Vachellerie, B. Borot, T. Devoivre, N. Bicaïs, B. Hinschberger, R. Pantel, N. Revil, C. Parthasarathy, N. Planes, H. Brut, J. Farkas***, J. Uginet, P. Stolk* and M. Woo*** STMicroelectronics, *Philips Semiconductors, **CEA-LETI and ***Motorola Inc., FRANCE 10:55 6A-2 Ultra-Low Power and High Speed SRAM for Mobile Applications Using Single Poly-Si Gate 90nm CMOS Technology Abstract K. Koh, B.J. Hwang, G.H. Han, K.H. Kwak, Y.S. Son, J.H. Jang, H.S. Kim, D. Park and K. Kim Samsung Electronics Co., Ltd., Korea (ROK) 11:20 6A-3 Robust Process Integration of 0.78µm2 Embedded SRAM with NiSi Gate and Low-K Cu Interconnect for 90nm SoC Applications Abstract Y.W. Kim, J.H. Ahn, T.S. Park, C.B. Oh, K.T. Lee, H.S. Kang, D.H. Lee, Y.G. Ko, K.S. Cheong, J.W. Jun, S.H. Liu, J. Kim, J.L. Nam, S.R. Ha, J.B. Park*, S.A. Song* and K.P. Suh Samsung Electronics and *Samsung Advance Institute of Technology, Korea 11:45 6A-4 Ultra Low Power 6T-SRAM Chip with Improved Transistor Performance and Reliability by HfO2-Al2O3 High-k Gate Dielectric Process Optimization Abstract C.-B. Oh, H.-J. Ryu, H.-S. Kang, M.-H. Oh, J.-H. Lee, N.-I. Lee, H.-W. Lee, C.-H. Jun, Y.-W. Kim and K.-P. Suh Samsung Electronics Co. Ltd., Korea back to conference schedule (Lunch 12:10-13:30) Wednesday, June 11 Session 6B DRAM/MIM Capacitor [Shunju II] Chairpersons W.-S. Lee, Samsung Electronics L. Tran, Micron Technology 10:30 6B-1 TiN/HfO2/TiN Capacitor Technology Applicable to 70nm Generation DRAMs Abstract S.-H. Oh, J.-H. Chung, J.-H. Choi, C.-Y. Yoo, Y.S. Kim, S.T. Kim, U.-I. Chung and J.T. Moon Samsung Electronics Co., Ltd., Korea 10:55 6B-2 A highly manufacturable 110nm EDRAM process with Al2O3 stack MIM capacitor for cost effective high density, high speed, low voltage ASIC memory applications Abstract F. Fishburn, R. Kauffman, R. Lane, T. McDaniel, K. Schofield, S. Southwick, R. Turi and H. Wang Micron Technology, USA 11:20 6B-3 HfO2 and Lanthanide-doped HfO2 MIM Capacitors for RF/Mixed IC Applications Abstract S.J. Kim, B.J. Cho, M.-F. Li, C. Zhu, A. Chin* and D.-L. Kwong** National University of Singapore, Singapore, *National Chiao Tung University, Taiwan, R.O.C. and **The University of Texas, USA 11:45 6B-4 Characterization and Comparison of High-k Metal-Insulator-Metal (MiM) Capacitors in 0.13 µm Cu BEOL for Mixed -Mode and RF Applications Abstract Y.L. Tu, H.L. Lin, L.L. Chao, D. Wu, C.S. Tsai, C. Wang, C.F. Huang, C.H. Lin and J. Sun Taiwan Semiconductor Manufacturing Corp. (TSMC), Taiwan back to conference schedule (Lunch 12:10-13:30) Wednesday, June 11 Session 7A High Performance Technology II [Shunju I] Chairpersons H. Tanaka, Oki Electric S. Thompson, Intel 13:30 7A-1 Thermally Robust Ta-Doped Ni SALICIDE Process Promising for sub-50nm CMOSFETs Abstract M.C. Sun, M.J. Kim, J.-H. Ku, K.J. Roh, C.S. Kim, S.P. Youn, S.-W. Jung, S. Choi, N.I. Lee, H.-K. Kang and K.P. Suh Samsung Electronics Co., Ltd., Korea (ROK) 13:55 7A-2 A 65nm-node CMOS Technology with Highly Reliable Triple Gate Oxide Suitable for power-considered System-on-a-Chip Abstract T. Fukai, Y. Nakahara, M. Terai, S. Koyama*, Y. Morikuni*, Y. Suzuki*, M. Nagase*, A. Mineji*, T. Matsuda*, T. Tamura*, F. Koba*, T. Onoda*, Y. Yamada*, M. Komori*, Y. Kojima*, Y Yama*, M. Ikeda*, T. Kudoh*, T. Yamamoto and K. Imai* NEC Corporation and *NEC Electronics Corporation, Japan 14:20 7A-3 A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer Abstract B. Hornung, R. Khamankar, H. Niimi, M. Goodwin, L. Robertson, D. Miles, B. Kirkpatrick, H. AlShareef, A. Varghese, M. Bevan, P. Nicollian, P.R. Chidambaram, S. Chakravarthi, A. Gurba, X. Zhang, J. Blatchford, B. Smith, J.P. Lu, J. Deloach, B. Rathsack, C. Bowen, G. Thakar, C. Machala and T. Grider Texas Instruments, USA 14:45 7A-4 90nm CMOS RF Technology with 9.0V I/O Capability for Single-Chip Radio Abstract G. Baldwin, J. Ai, K. Benaissa, F. Chen, P.R. Chidambaram, S. Ekbote, S. Ghneim, S. Liu, C. Machala, F. Mehrad, D. Mosher, G. Pollack, T. Tran, B. Williams, J. Yang, S. Yang and F.S. Johnson Texas Instruments, USA back to conference schedule (Break 15:10-15:30) Wednesday, June 11 Session 7B Nonvolatile Memory II [Shunju II] Chairpersons S. Onishi, Sharp D. Shum, Infineon Technologies 13:30 7B-1 A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs Abstract M. Ichige, Y. Takeuchi, K. Sugimae, A. Sato, M. Matsui, T. Kamigaichi, H. Kutsukake, Y. Ishibashi, M. Saito, S. Mori, H. Meguro, S. Miyazaki, T. Miwa, S. Takahashi, T. Iguchi, N. Kawai, S. Tamon, N. Arai, H. Kamata, T. Minami, H. Iizuka, M. Higashitani*, T. Pham*, G. Hemink*, M. Momodomi and R. Shirota Toshiba Corp., Japan and *SanDisk Corporation, USA 13:55 7B-2 Highly Manufacturable 90nm NOR Flash Technology with 0.081µm2 Cell Size Abstract Y. Song, S. Lee, T. Kim, J. Han, H. Lee, S. Kim, J. Park, S. Park, J. Choi, J. Kim, D. Lee, M. Cho, K. Park and K. Kim Samsung Electronics Co.,LTD., Korea(ROK) 14:20 7B-3 New Single-poly EEPROM with Cell Size down to8F2 for High Density Embedded Nonvolatile Memory Applications Abstract K.-H. Lee and Y.-C. King National Tsing-Hua University, Taiwan, R.O.C. 14:45 7B-4 New Buried Bit-line NAND (BiNAND) Flash Memory for Data Storage Abstract S. Chang, E. Yang*, T. Chen, L. Huang, B. Hsu, D. Sung**, J.-C. Duh**, C.-W. Hung**, V. Huang**, Y.-C. King*, C.-H. Chu and C.C.-H. Hsu eMemory Technology Incorporation, *National Tsing-Hua University and **Powerchip Semiconductor Corporation, Taiwan, R.O.C. back to conference schedule (Break 15:10-15:30) Wednesday, June 11 Session 8A Strained Silicon MOSFET [Shunju I] Chairpersons Y. Omura, Kansai Univ. K. De Meyer, IMEC 15:30 8A-1 (110)-Surface Strained-SOI CMOS Devices with Higher Carrier Mobility Abstract T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai and S. Takagi Association of Super-Advanced Electronics Technology (ASET), Japan 15:55 8A-2 Ultra-thin Strained-SOI CMOS for High Temperature Operation Abstract T. Maeda, T. Mizuno*, N. Sugiyama*, T. Tezuka*, T. Numata*, J. Koga* and S. Takagi* National Institute of Industrial Science and Technology (ASRC-AIST) and *Association of Super-Advanced Electronics Technology (ASET), Japan 16:20 8A-3 Strained Silicon NMOS with Nickel-Silicide Metal Gate Abstract Q. Xiang, J.-S. Goo, J. Pan, B. Yu, S. Ahmed, J. Zhang and M.-R. Lin Advanced Micro Devices, Inc., USA 16:45 8A-4 Performance of 70nm Strained-Silicon CMOS Devices Abstract J.R. Hwang, J.H. Ho, S.M. Ting, T.P. Chen, Y.S. Hsieh, C.C. Huang, Y.Y. Chiang, H.K. Lee, A. Liu, T.M. Shen, G. Braithwaite*, M. Currie*, N. Gerrish*, R. Hammond*, A. Lochtefeld*, F. Singaporewala*, M. Bulsara*, Q. Xiang**, M.R. Lin**, W.T. Shiau, Y.T. Loh, J.K. Chen, S.C. Chien and F. Wen UMC, Taiwan, *AmberWave Systems and **AMD, USA back to conference schedule Wednesday, June 11 Session 8B Multilevel Interconnects I [Shunju II] Chairpersons H. Oyamatsu, Toshiba C.-S. Pai, Lucent Technologies 15:30 8B-1 Advanced 300mm Cu/CVD LK (k=2.2) Multilevel Damascene Integration for 90/65nm Generation BEOL Interconnect Technologies Abstract L.P. Li, Y.C. Lu, H.H. Lu, Y.L. Yang, C.H. Lin, K.C. Lin, B.T. Chen, M. Liang, S.M. Jang and M.S. Liang Taiwan Semiconductor Manufacturing Company, Taiwan, R.O.C. 15:55 8B-2 Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SiOC Hybrid Structure for 65nm-node High Performance eDRAM Abstract R. Kanamura, Y. Ohoka, M. Fukasawa, K. Tabuchi, K. Nagahata, S. Shibuki, M. Muramatsu, H. Miyajima*, T. Usui*, A. Kajita*, H. Shibata* and S. Kadomura Sony Corporation and * Toshiba Corporation, Japan 16:20 8B-3 High Performance/Reliability Cu Interconnect with Selective CoWP Cap Abstract T. Ko, C.L. Chang, S.W. Chou, M.W. Lin, C.J. Lin, C.H. Shih, H.W. Su, M.H. Tsai, W.S. Shue and M.S. Liang Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), R.O.C. 16:45 8B-4 Accurate Modeling Method for Deep Sub-Micron Cu Interconnect Abstract K. Yamada, N. Okada, M. Yasuda and N. Oda NEC Electronics Corporation, Japan back to conference schedule Wednesday, June 11 20:00-22:00 Rump Sessions Organizers K. Shibahara, Hiroshima Univ. C.-S. Pai, Lucent Technologies J-R Judgement Day for Power Management Organizers   T. Hiramoto; Univ. of Tokyo   T. Kawahara,   Hitachi   K. Bernstein,   IBM   P. Rickert,   Texas Instruments Moderators   S. Natarajan,   ATMOS/MOSYS   P. Rickert, ; Texas Instruments Dear Circuit, Architecture, and Device/Process Panelist Vice Presidents:  Our audience shareholders will be meeting in a VLSI Symposium panel discussion session this year to decide which of your three teams has made the most important contributions towards resolving the urgent ULSI power consumption crisis, and which of you needs to be replaced. Both dynamic and static power is out of control, and we can no longer accept your promises. Each of you will be given a brief opportunity to defend your discipline's past achievements and to describe your plans for the next technology generation. You then will face your shareholder's questions and complaints. The meeting will conclude with a shareholder decision of who gets the promotion to CTO, who receives more worthless stock options, and who starts a new career in marketing. R-1 High-k Gate Dielectrics: Are They Put in Practical Use at Suitable Time? Moderators   M. Niwa,   Matsushita   G. Wilk,   ASM Despite the rapidly growing demand for high-k materials in gate dielectric applications, fundamental challenges remain to be conquered. In this session, we will address some of the key issues from the perspective of the following questions, and discuss whether the intrinsic high-k dielectric problems can be overcome, or whether they are insuperable. 1. What is the most crucial problem to be overcome for high-k gate dielectrics? Is it intrinsic or extrinsic? 2. Is the manufacturing high-k material more likely to be a binary (e.g. HfO2) or ternary (e.g. HfSiO or HfAlO) based system (not including N)? How important is the morphology (amorphous vs. crystalline)? Can the material be different for low-power and high-performance devices? 3. What are the major issues for integrating poly-Si with high-k gate dielectrics? 4. Which process is most likely to be used for high-k manufacturing (CVD,ALD,PVD, others)? 5. What node and in what kind of devices (low power vs. high performance) will high-k first be introduced, and will the gate material be poly-Si or metal? 6. What is the origin of mobility degradation at both low and high fields, and is it necessary to improve the mobility at lower electric field? 7. Is reliability a major concern for high-k gate dielectrics? 8. What alternatives are most likely if the introduction of the high-k with poly-Si for planar bulk CMOS is delayed, and can high-k be integrated into alternative stacks or structures beyond 65 nm? R-2 Interconnecting Interconnect Technology and Packaging Moderators   T. Ohba,   Fujitsu   K. Maex,   IMEC The on chip wiring technology counts on low k values for the dielectrics and reliable narrow lines with low resistivity. Can TOFU-like low k materials, i.e. with low mechanical strength and adhesion be processed and packaged? Can one manufacture wiring with sufficient density and low resistivity? Can packaging technology be helping out by providing low cost technology for global communication on the chip? Can advanced packaging technologies provide solutions by 3D integration? In short: do we envision a limitation of manufacturing and/or further scaling at the coming 45nm node or can we go further by interconnecting interconnect technology and packaging? R-3 Embedded Non-Volatile Memories - What eNVM Technologies Will Dominate the SoC Memory Markets in the Next 10 Years? Moderators   H. Kuroda,   Sony   D. Shum,   Infineon One of the dominant factor of the past decade in SoC markets has been the explosive growth of the embedded memories, notably eNVM products driven by Smartcard/Security card, µcontroller in automotive, cellular phones, and other types of consumer or portable electronics. Densities are broad, ranging from few bits/low cost consumer electronics to high density/low power portable communications. The current eNVM technologies are derived from stand-alone FG concept, from ETOX with injection mechanism to tunneling such as EEPROM. These technologies have limitations in endurance and retention, slow W/E operations. High voltages are required for W/E operation; making the scaling very difficult. Typically 8-12 extra masks over logic process; making high cost to the end products. A number of new elements or architectures have been introduced as well as some enhancements have been made to the cell operation to achieve scaling. Multi-level cell approaches have not yet demonstrated for embedded applications. Additionally, industrial interest is growing rapidly for new technologies that exploit new materials or storage concepts like discrete traps (SONOS), polarization in ferroelectrics (FeRAM), chalcogenide phase change, and electron spin in magnetic (MRAM). This rump session will feature various industry experts on current eNVM FG-technologies and comments from potential customers, compare the different approaches in terms of the main parameters such as bit-size, cost & scalability, reliability, W/E time, power consumptions, high performance, and potential applications from such technologies. The emerging eNVM technologies (MRAM, FeRAM, PCRAM and SONOS) will also be discussed with potential market applications. back to conference schedule Thursday, June 12 Session 9A Advanced CMOS I [Shunju I] Chairpersons K. Sakamoto, AIST Y. Ponomarev, Philips Research Leuven 8:30 9A-1 Re-examination of Subband Structure Engineering in Ultra-Short Channel MOSFETs under Ballistic Carrier Transport Abstract S. Takagi Toshiba Corporation, Japan 8:55 9A-2 Germanium MOS: An Evaluation from Carrier Quantization and Tunneling Current Abstract T. Low, Y.T. Hou, M.F. Li, C. Zhu, D.-L. Kwong* and A. Chin** National University of Singapore, Singapore, *University of Texas at Austin, USA and **National Chiao Tung Univ., Taiwan 9:20 9A-3 Very Low Defects and High Performance Ge-On-Insulator p-MOSFETs with Al2O3 Gate Dielectrics Abstract C.H. Huang, M.Y. Yang, A. Chin, W.J. Chen*, C.X. Zhu**, B.J. Cho**, M.-F. Li** and D.L. Kwong*** National Chiao Tung Univ., *National Yun-Lin Polytechnic Inst., Taiwan, **National Univ. of Singapore, Singapore and ***The Univ. of Texas, USA 9:45 9A-4 Ge MOS Characteristics with CVD HfO2 Gate Dielectrics and TaN Gate Electrode Abstract W.P. Bai, N. Lu, J. Liu, A. Ramirez*, D.L. Kwong, D. Wristers*, A. Ritenour**, L. Lee** and D. Antoniadis** University of Texas, *Advanced Micro Devices and **MIT, USA back to conference schedule (Break 10:10-10:30) Thursday, June 12 Session 9B Multilevel Interconnects II [Shunju II] Chairpersons Y. Takao, Fujitsu S. Yeh, LSI Logic 8:30 9B-1 Novel CMP Slurries for Planarization of Multilevel Copper Interconnect Abstract J.Y. Song, Y.H. Chen, S.N. Lee, W.C. Chiou, T.C. Tseng, H.H. Kuo, C.J. Chuang, K.C. Lin, S.M. Jang and M.S. Liang Taiwan Semiconductor Manufacturing Company, Taiwan, R.O.C. 8:55 9B-2 Impacts of High Modulus Ultra Low-k/Cu 300 mm-wafer Integration for 65 nm Technology Node and Beyond Abstract S. Sone, N. Ohashi, H.J. Shin, K. Misawa, N. Kaji, K. Inukai, A. Matsushita, K. Sudou, S. Tokitoh, S. Kondo, B.U. Yoon, K. Yoneda, T Yoshie, N. Ohtsuka, H. Okamura, Y. Toyoda, F. Shoji, T. Nasuno, M. Shimada, S. Ogawa, I. Matsumoto and N. Kobayashi Semiconductor Leading Edge Technologies, Inc. (Selete), Japan 9:20 9B-3 Thermally robust 90nm node Cu-Al wiring technology using solid phase reaction between Cu and Al Abstract Y. Matsubara, M. Komuro, T. Onodera, N. Ikarashi, Y. Hayashi and M. Sekine NEC Electronics Corporation, Japan 9:45 9B-4 A HSQ-based Inorganic Sacrificial Via Filler-assisted 90 nm-node Cu/Low-k OSG Dual Damascene Process Integration Abstract K.-W. Lee, S.G. Lee, W.J. Park, B.J. Oh, J.H. Kim, S.J. Lee, K.K Park, I.G. Kim, J.H. Chung, K.T. Lee, Y.J. We, W.S. Song, S.R. Hah, H.-K. Kang and K.-P. Suh Samsung Electronics Co., Ltd., KOREA back to conference schedule (Break 10:10-10:30) Thursday, June 12 Session 10A Advanced CMOS II [Shunju I] Chairpersons H. Wakabayashi, NEC M.-R. Lin, AMD 10:30 10A-1 High Performance 25nm FDSOI Devices with Extremely Thin Silicon Channel Abstract Z. Krivokapic, W. Maszara, F. Arasnia, E. Paton, Y. Kim*, L. Washington*, E. Zhao, J. Chan, J. Zhang, A. Marathe and M.-R. Lin AMD and *Applied Materials, USA 10:55 10A-2 Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout Abstract B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios and R. Chau Intel Corporation, USA 11:20 10A-3 Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers Abstract T. Park, S. Choi, D.H. Lee, J.R. Yoo, B.C. Lee, J.Y. Kim, C.G. Lee, K.K. Chi, S.H. Hong, S.J. Hyun, Y.G. Shin, J.N. Han, I.S. Park, U.I. Chung, J.T. Moon, E. Yoon* and J.H. Lee** Samsung Electronics Co., Ltd., *Seoul National University and **Kyungpook National University, Korea 11:45 10A-4 Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling Abstract F.-L. Yang, H.-Y. Chen, C.-C. Huang, C.-H. Ge, K.-W. Su, C.-C. Huang, C.-Y. Chang, D.-W. Lin, C.-C. Wu, J.-K. Ho, W.-C. Lee, Y.-C. Yeo, C.H. Diaz, M.-S. Liang, J.Y.-C. Sun and C. Hu Taiwan Semiconductor Manufacturing Company, TAIWAN, ROC back to conference schedule (Lunch 12:10-13:30) Thursday, June 12 Session 10B Gate Dielectric Technology [Shunju II] Chairpersons T. Ipposhi, Mitsubishi Electric S.Venkatesan, Motorola 10:30 10B-1 Experimental Evidence for the Generation of Bulk Traps by Negative Bias Temperature Stress and Their Impact on the Integrity of Direct-tunneling Gate Dielectrics Abstract S. Tsujikawa, K. Watanabe, R. Tsuchiya, K. Ohnishi and J. Yugami Hitachi, Ltd., Japan 10:55 10B-2 Remote Plasma-Enhanced Atomic Layer Deposition (RPEALD) Nitride/Oxide Gate Dielectric for Sub-65nm Low Standby Power CMOS Application Abstract C.-C. Chen, T.-L. Lee, D.-Y. Lee*, V.S. Chang, H.-C. Lin**, S.-C. Chen, T.-Y. Huang* and M.-S. Liang Taiwan Semiconductor Manufacturing Co. Ltd., *National Chiao Tung University and **National Nano Device Laboratory, Taiwan, R.O.C. 11:20 10B-3 Low-energy Nitrogen Plasma for 65-nm node Oxynitride Gate Dielectrics: A Correlation of Plasma Characteristics and Device Parameters Abstract P.A. Kraus, K. Ahmed, T.C. Chua, M. Ershov*, H. Karbasi*, C.S. Olsen, F. Nouri, J. Holland, R. Zhao, G. Miner and A. Lepert Applied Materials, Inc. and *PDF Solutions, Inc., U.S.A. 11:45 10B-4 Impact of Oxygen-enriched SiN Interface on Al2O3 Gate Stack An Innovative Solution to Low-power CMOS Abstract S. Saito, Y. Shimamoto, S. Tsujikawa, H. Hamamura, O. Tonomura, D. Hisamoto, T. Mine, K. Torii, J. Yugami, M. Hiratani, T. Onai and S. Kimura Hitachi Ltd., Japan back to conference schedule (Lunch 12:10-13:30) Thursday, June 12 Session 11A Damascene and Metal Gate Technology [Shunju I] Chairpersons K. Shibahara , Hiroshima Univ. J. Wu, Texas Instruments 13:30 11A-1 Highly Manufacturable Sub-50 nm High Performance CMOSFET Using Real Damascene Gate Process Abstract C.-W. Oh, S.-H. Kim, C.-S. Lee, J.-D. Choe, S.-A. Lee, S.-Y. Lee, K.-H. Yeo, H.-J. Jo, E.-J. Yoon, S.-J. Hyun, D. Park and K. Kim Samsung Electronics Co., KOREA 13:55 11A-2 A Novel Approach for Integration of Dual Metal Gate Process Using Ultra Thin Aluminum Nitride Buffer Layer Abstract C.S. Park, B.J. Cho, D.A. Yan*, N. Balasubramanian* and D.-L. Kwong* National University of Singapore, Singapore and *The University of Texas, USA 14:20 11A-3 Robust HfN Metal Gate Electrode for Advanced MOS Devices Application Abstract H.Y. Yu, H.F. Lim, J.H. Chen, M.F. Li, C.X. Zhu, D.-L. Kwong*, C.H. Tung**, K.L. Bera** and C.J. Leo** National University of Singapore, Singapore, *University of Texas at Austin, USA and **Institute of Microelectronics, Singapore back to conference schedule (Break 14:45-15:05) Thursday, June 12 Session 11B Process Technology [Shunju II] Chairpersons Y. Tada, Tokyo Electron S. Yeh, LSI Logic 13:30 11B-1 A Novel NF3-HDP-CVD Process for STI-Filling in Sub-90nm DRAM and Beyond Abstract Y.-W. Cha, S.-H. Rha, W.-J. Kim, K.-T. Na, U.-I. Chung and J.-T. Moon Samsung Electronics Co., LTD., Korea 13:55 11B-2 The P-SOG Filling Shallow Trench Isolation Technology for sub-70nm Device Abstract J.-H. Heo, S.-J. Hong, G.-H. Yon, Y.-G. Shin, K. Fujihara, U.-I. Chung and J.-T. Moon Samsung Electronics Co., Ltd., Korea 14:20 11B-3 Novel Co/Ni Bi-layer Salicidation for 45nm Gate Technology Abstract M.Y. Wang, C.W. Chang, C.M. Wu, C.T. Lin, C.H. Hsieh, W.S. Shue and M.S. Liang Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan, R.O.C. back to conference schedule (Break 14:45-15:05) Thursday, June 12 Session 12A High-K Gate Dielectric II [Shunju I] Chairpersons M. Niwa, Matsushita Electric P. Zeitzoff, International SEMATECH 15:05 12A-1 Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics Abstract A. Kerber, E. Cartier*, L.Å. Ragnarsson**, M. Rosmeulen**, L. Pantisano**, R. Degraeve**, Y. Kim*** and G. Groeseneken** Infineon Technologies AG, *IBM Research Division, **IMEC and ***International Sematech, Belgium 15:30 12A-2 Energy Distribution of Interface Traps in High-K Gated MOSFETs Abstract J.-P. Han, E.M. Vogel, E.P. Gusev*, C. D'Emic*, C.A. Richter, D.W. Heh and J.S. Suehle National Institute of Standards and Technology and *IBM Semiconductor Research and Development Center, USA 15:55 12A-3 Dynamics of Threshold Voltage Instability in Stacked High-k Dielectrics: Role of the Interfacial Oxide Abstract L. Pantisano, E. Cartier*, A. Kerber**, R. Degraeve, M. Lorenzini, M. Rosmeulen, G. Groeseneken and H.E. Maes IMEC, *IBM and **Infineon Technologies, Belgium 16:20 12A-4 High mobility MISFET with low trapped charge in HfSiO films Abstract A. Morioka, H. Watanabe, M. Miyamura, T. Tatsumi, M. Saitoh, T. Ogura, T. Iwamoto, T. Ikarashi, Y. Saito, Y. Okada, H. Watanabe, Y. Mochiduki and T. Mogami NEC corporation, Japan 16:45 12A-5 Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer Abstract Y. Kim, C. Lim, C.D. Young, K. Matthews, J. Barnett, B. Foran, A. Agarwal, G.A. Brown, G. Bersuker, P. Zeitzoff, M. Gardner, R.W. Murto, L. Larson, C. Metzner*, S. Kher* and H.R. Huff International SEMATECH (ISMT) and *Applied Materials, U.S.A. back to conference schedule Thursday, June 12 Session 12B Advanced Memory [Shunju II] Chairpersons T. Nakamura, Rohm C. Dennison, Ovonyx 15:05 12B-1 Highly Manufacturable and Reliable 32Mb FRAM Technology with Novel BC and Capacitor Cleaning Process Abstract Y.J. Song, H.J. Joo, N.W. Jang, H.H. Kim, J.H. Park, H.Y. Kang, S.Y. Lee and K. Kim Samsung Electronics Co. Ltd., Korea 15:30 12B-2 0.18µm SBT-Based Embedded FeRAM Operating at a Low Voltage of 1.1V Abstract Y. Nagano, T. Mikawa, T. Kutsunai, S. Hayashi, T. Nasu, S. Natsume, T. Tatsunari, T. Ito, S. Goto, H. Yano, A. Noma, K. Nagahashi, T. Miki, M. Sakagami, Y. Izutsu, T. Nakakuma, H. Hirano, S. Iwanari, Y. Murakuki, K. Yamaoka, Y. Goho, Y. Judai, E. Fujii and K. Sato Matsushita Electric Industrial Co., Ltd., Japan 15:55 12B-3 Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24µm-CMOS Technologies Abstract Y.N. Hwang, J.S. Hong, S.H. Lee, S.J. Ahn, G.T. Jeong, G.H. Koh, J.H. Oh, H.J. Kim, W.C. Jeong, S.Y. Lee, J.H. Park, K.C. Ryoo, H. Horii, Y.H. Ha, J.H. Yi, W.Y. Cho, Y.T. Kim, K.H. Lee, S.H. Joo, S.O. Park, U.I. Chung, H.S. Jeong and K. Kim Samsung Electronics Co., Ltd, Korea 16:20 12B-4 An Edge Contact Type Cell for Phase Change RAM Featuring Very Low Power Consumption Abstract Y.H. Ha, J.H. Yi, H. Horii, J.H. Park, S.H. Joo, S.O. Park, U.-I. Chung and J.T. Moon Samsung Electronics Co., Ltd., Korea 16:45 12B-5 A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM Abstract H. Horii, J.H. Yi, J.H. Park, Y.H. Ha, I.G. Baek, S.O. Park, Y.N. Hwang, S.H. Lee, Y.T. Kim, K.H. Lee, U.-I. Chung and J.T. Moon Samsung Electronics Co., Ltd., Korea back to conference schedule