Welcome to the 2007 Symposium on VLSI Circuits
“Twentieth Anniversary”
You are cordially invited to attend the 2007 Symposium on VLSI
Circuits, to be held on June 14-16th, 2007, at the Rihga Royal Hotel
Kyoto in Kyoto, Japan. The Symposium will mark its twentieth
anniversary of the first Circuit Symposium. Following the tradition,
the Symposium on VLSI Circuits will follow the Symposium on
VLSI Technology at the same location. The Symposium has
established itself as a major international forum for presenting and
exchanging important ideas and new developments in VLSI circuit
design. We have expanded the digital-field scope to include largescale
system level issues as they affect cross-layer circuit
integration, in addition to Analog, Digital, Memory, Signal
Processing, and Communications Circuits. Contributions to the
Symposium come from both industry and academia around the
world.
Preceding the Symposium on June 13th, a one-day Short Course will
be held. This short course will focus on “Design for Variability in
Logic, Memory and Microprocessors” where experts will give
educational talks on this timely topic in VLSI circuits. On the same
day, we have a Workshop on “Advanced Topics on Multi-Standard
Wireless Transceiver RFIC Designs.” With a single Short
Course/Workshop registration fee you can select to attend either
session. This year, the technical program committee reviewed 343
papers, which is record high for Kyoto Symposium, and selected 103
papers for presentation. The core tradition of the Symposium is the
paper quality and this year the committee has selected very high
quality papers representing the scope of the symposium. We have
also invited four distinguished speakers to describe recent advances
and new challenges in the areas of future mobile phones, analog
power consumption, microprocessors for game consoles, and organic
electronics. To complement the formal talks, we have arranged four
evening rump sessions on interesting and provocative subjects to
give you an opportunity to participate in the discussions and mix
with the participants. The rump sessions explore: “Analog Scaling
and SOC integration”, “CMOS Scaling: Where will Economics Set
the End of the Line?”, and “Are Design Tools and Methodologies
Measuring up to the Challenge of the DFM Era?”. The rich technical
content of the program will undoubtedly interest you, and we
certainly hope that the Symposium will be a fruitful and enjoyable
experience. This booklet contains the advance program together with
forms for the Symposium registration and hotel reservations. Please
complete and return these forms or visit our website for online
registration at http://www.vlsisymposium.org/symposia.html.
Although on-site registration will be available at the conference, preregistration
will facilitate Symposium planning. We look forward to
meeting with you at the Symposium in Kyoto.
|
Kazuo Yano |
Katsu Nakamura |
| Program Chair |
Program Co-Chair |
CONFERENCE SCHEDULE
Tuesday, June 12 |
8:00-17:00 |
Registration |
| Wednesday, June 13 |
7:00 |
Breakfast |
| 7:30 |
Registration |
| 8:10-12:00 |
Short Course [Suzaku II] / Workshop [Suzaku III] |
| 13:30-18:00 |
Short Course [Suzaku II] / Workshop [Suzaku III] |
| 18:00-20:00 |
Reception [Suzaku I] |
| 20:00-22:00 |
Technology and Circuits Joint Rump Session [Suzaku] |
| Thursday, June 14 |
7:00 |
Breakfast |
| 8:00 |
Registration |
| 8:30-10:15 |
Session 1 |
Welcome and Plenary Session I [Suzaku] |
| 10:40-12:20 |
Session 2 |
Configurable and Reconfigurable SoCs [Suzaku I] |
| Session 3 |
Power Management [Suzaku II] |
| Session 4 |
Multi-Gb/s Receivers and Transmitters
[Suzaku III] |
| 13:40-15:20 |
Session 5 |
High Performance Processing [Suzaku I] |
| Session 6 |
High Speed Wireless Communication [Suzaku II] |
| Session 7 |
High Speed Data Converters [Suzaku III] |
| 15:35-17:40 |
Session 8 |
Fuse Memories and SRAM Design Challenges
[Suzaku I] |
| Session 9 |
Low Power Wireless Communication [Suzaku II] |
| Session 10 |
Analog Techniques [Suzaku III] |
| 20:00-22:00 |
Rump Sessions [Suzaku I,II,III] |
| Friday, June 15 |
7:00 |
Breakfast |
| 8:30-10:00 |
Session 11 |
Plenary Session II [Shunju I, II] |
| 10:30-12:10 |
Session 12 |
Techniques for Signal and Power Integrity
[Shunju I] |
| Session 13 |
High Speed Wireline [Shunju II] |
| Session 14 |
Sensors and Display [Shunju III] |
| 13:30-15:10 |
Session 15 |
Low Power Circuit Techniques [Shunju I] |
| Session 16 |
Clock Generators and Time-to-Digital
Converters
[Shunju II] |
| Session 17 |
MM-Wave Building Blocks [Shunju III] |
| 15:25-17:30 |
Session 18 |
Dynamic & Nonvolatile Memories
[Shunju I] |
| Session 19 |
Nyquist Data Converters [Shunju II] |
| Session 20 |
Tuners/Receiver and RF test [Shunju III] |
| 18:00-20:00 |
Dinner [Suzaku] |
| Saturday, June 16 |
7:00 |
Breakfast |
| 8:30-10:35 |
Session 21 |
Processors for Mobile Applications [Shunju I] |
| Session 22 |
Advanced DLL and PLLs [Shunju II] |
| Session 23 |
Oversampled Data Converters [Shunju III] |
| 10:50-12:30 |
Session 24 |
Embedded SRAMs [Shunju I] |
| Session 25 |
Frequency Synthesizer [Shunju II] |
| Session 26 |
High Bit Rate Wireline [Shunju III] |
PROGRAM
Joint Rump Session with Technology
|
J-R |
Are Design Tools and Methodologies Measuring up to the
Challenges of the DFM Era? |
| Organizers |
S. Odanaka, Osaka University
R. Rios, Intel
S. Kumashiro, NEC Electronics
A. Bhavnagarwala, IBM |
| Moderators |
M. Hane, NEC
K. Zhang, Intel |
Panelists |
H. Masuda, Renesas
M. Patyra, Intel
C. Radens, IBM
A. Amerasekera, Texas Instruments
J. Farrell, AMD
H. Yoshimura, Toshiba |
Compact models play a key role in DFM era, especially in
variability-aware LSI design. There are questions as to the
capabilities of these models, effectiveness in design, and credibility
when design is concurrent with process development. The panel
addresses some key questions.
- Are empirical Spice models sufficient or do we need to invest on
better physical models for new materials and device architecture?
- Can we trust these models calibrated with limited process data?
- How do we accurately account for variations when design is
concurrent to process development?
- How do we properly distinguish between systematic and random
variations?
- Can we trust physical OPC, etching, and CMP models for
predictions?
- Do the Spice variation models even matter when there are so many
other sources of errors such as tool limitations, crude static timing
assumptions, MCF approximations, and the exclusion of MIS and
crosstalk? |
Session 1 |
Welcome and Plenary Session I [Suzaku] |
| Chairpersons |
K. Yano, Hitachi, Ltd.
K. Nakamura, Analog Devices, Inc. |
8:30 |
1-1 |
Welcome and Opening Remarks |
|
|
T. Kuroda, Keio Univ.
S. Kosonocky, IBM |
8:45 |
1-2 |
Mobile Terminals toward LTE and Requirements
on Device Technologies |
|
Invited |
S. Maruyama, NTT Docomo |
9:30 |
1-3 |
Limits of Power Consumption in Analog Circuits |
|
Invited |
H.-S. Lee, Massachusetts Institute of Technology |
Session 2 |
Configurable and Reconfigurable SoCs [Suzaku I] |
| Chairpersons |
K. Kobayashi, Kyoto Univ.
K. Nowka, IBM Austin Research Laboratory |
10:40 |
2-1 |
A 1.41W H.264/AVC Real-Time Encoder SOC for
HDTV1080P |
|
Abstract |
Z. Liu*, Y. Song*, M. Shao*, S. Li*, L. Li*,
S. Ishiwata**, M. Nakagawa**, S. Goto* and
T. Ikenaga* |
| *Waseda University and **Toshiba Corporation,
Japan |
11:05 |
2-2 |
Design of a Multi-Core SoC with Configurable
Heterogeneous 9 CPUs and 2 Matrix Processors |
|
Abstract |
M. Nakajima, H. Kondo, N. Okumura, N. Masui,
Y. Takata, T. Nasu, H. Takata, T. Higuchi,
M. Sakugawa, H. Yoneda, H. Fujiwara, K. Ishida,
K. Ishimi, S. Kaneko, T. Itoh, M. Sato, O. Yamamoto
and K. Arimoto |
| Renesas Technology Corp., Japan |
11:30 |
2-3 |
A 19-mode 8.29mm2 52-mW LDPC Decoder Chip
for IEEE 802.16e System |
|
Abstract |
X.-Y. Shih, C.-Z. Zhan, C.-H. Lin and A.-Y. Wu |
| National Taiwan University, Taiwan |
11:55 |
2-4 |
Heterogeneous Multiprocessor on a Chip Which
Enables 54x AAC-LC Stereo Encoding |
|
Abstract |
M. Ito*,***, T. Todaka*, T. Tsunoda*, H. Tanaka*,
T. Kodama*, H. Shikano*,***, M. Onouchi*,
K. Uchiyama*,***, T. Odaka*,***, T. Kamei**,
E. Nagahama**, M. Kusaoke**, Y. Nitta**,
Y. Wada***, K. Kimura*** and H. Kasahara*** |
| *Hitachi, Ltd., **Renesas Technology Corp. and
***Waseda University, Japan |
Session 3 |
Power Management [Suzaku II] |
| Chairpersons |
M. Song, Dongguk Univ.
B. Zhao, Freescale Semiconductor |
10:40 |
3-1 |
A High Efficiency DC-DC Converter Using 2nH
On-Chip Inductors |
|
Abstract |
J. Wibben and R. Harjani |
| University of Minnesota, USA |
11:05 |
3-2 |
A 100μA Digital Controller with Transient
Enhancement for Dynamic Voltage Output
Switching-type DC-DC Converter |
|
Abstract |
C.-Y. Tseng and P.-C. Huang |
| National Tsing Hua University, Taiwan |
11:30 |
3-3 |
A Delay Locked Loop Synchronization Scheme for
High Frequency Multiphase Hysteretic DC-DC
Converters |
|
Abstract |
P. Li*, R. Bashirullah*, P. Hazucha** and T. Karnik** |
| *University of Florida and **Intel Labs, USA |
11:55 |
3-4 |
An Ultra Fast Fixed Frequency Buck Converter
with Maximum Charging Current Control and
Adaptive Delay Compensation for DVS
Applications |
|
Abstract |
F. Su, W.-H. Ki and C.-Y. Tsui |
| The Hong Kong University of Science and Technology,
China |
Session 4 |
Multi-Gb/s Receivers and Transmitters [Suzaku III] |
| Chairpersons |
M. Nagata, Kobe Univ.
A. Amerasekera, Texas Instruments |
10:40 |
4-1 |
A 14-Gb/s 32 mW AC Coupled Receiver in 90-nm
CMOS |
|
Abstract |
M. Hossain and A.C. Carusone |
| University of Toronto, Canada |
11:05 |
4-2 |
A 5.2Gbps HyperTransportTM Integrated AC
Coupled Receiver with DFR DC Restore |
|
Abstract |
E. Fang, G. Asada, R. Kumar, S. Hale and M. Leary |
| Advanced Micro Devices, USA |
11:30 |
4-3 |
BER-based Adaptation of I/O Link Equalizers
|
|
Abstract |
E-H. Chen*, J. Ren**, J. Zerbe**, B. Leibowitz**,
H. Lee**, V. Stojanovi´c**,*** and C.-K.K. Yang* |
| *University of California, **Rambus, Inc and
***Massachusetts Institute of Technology, USA |
11:55 |
4-4 |
A 24Gb/s Software Programmable Multi-Channel
Transmitter |
|
Abstract |
A. Amirkhany*, A. Abbasfar**, J. Savoj**,
M. Jeeradit**, B. Garlepp**, V. Stojanovic**,*** and
M. Horowitz*,** |
| *Stanford University, **Rambus Inc. and
***Massachusetts Institute of Technology, USA |
Session 5 |
High Performance Processing [Suzaku I] |
| Chairpersons |
M. Hariyama, Tohoku Univ.
J.Farrell, Advanced Micro Devices |
13:40 |
5-1 |
A 5.1GHz 0.34mm2 Router for Network-on-Chip
Applications |
|
Abstract |
S. Vangal*,**, A. Singh*, J. Howard*, S. Dighe*,
N. Borkar* and A. Alvandpour** |
| *Intel Corporation, USA and **Linköping University,
Sweden |
14:05 |
5-2 |
RF2 : A 1GHz FIR Filter with Distributed
Resonant Clock Generator |
|
Abstract |
V.S. Sathe, J.C. Kao and M.C. Papaefthymiou |
| University of Michigan, USA |
14:30 |
5-3 |
A 6.5GHz 54mW 64-bit Parity-Checking Adder for
65nm Fault-Tolerant Microprocessor Execution
Cores |
|
Abstract |
S. Mathew, M. Anders, R. Krishnamurthy and S. Borkar |
| Intel Corp., USA |
14:55 |
5-4 |
A Design Methodology Realize an Over GHz
Synthesizable Streaming Processing Unit |
|
Abstract |
K. Ueno, H. Murakami, N. Yano, R. Okuda,
T. Himeno, T. Kamei and Y. Urakawa |
| Toshiba Corporation Semiconductor Company, Japan |
Session 6 |
High Speed Wireless Communication [Suzaku II] |
| Chairpersons |
K. Agawa, Toshiba Corp.
A. Abidi, Univ. of California |
13:40 |
6-1 |
A 9-Bit 6.3GHz 2.5W Quadrature Direct Digital
Synthesizer MMIC |
|
Abstract |
X. Yu*, F.F. Dai*,**, D. Yang*, V. Kakani*,
J.D. Irwin* and R.C. Jaeger* |
| *Auburn University and **Amtec Corporation, USA |
14:05 |
6-2 |
A 2-GHz Direct Sampling Delta-Sigma Tunable
Receiver with 40-GHz Sampling Clock and On-chip
PLL |
|
Abstract |
T. Chalvatzis*, T.O. Dickson*,** and
S.P. Voinigescu* |
| *University of Toronto, Canada and **IBM T. J.
Watson Research Center, USA |
14:30 |
6-3 | A 2.2 Gb/s DQPSK Baseband Receiver in 90-nm
CMOS for 60 GHz Wireless Links |
|
Abstract |
M. Chen and M.-C.F. Chang |
| University of California, Los Angeles, USA |
14:55 |
6-4 |
A 108/98 pJ/b 1Gbps Fully Integrated Interference
Tolerant Frequency Channelized UWB
Transmitter/Receiver |
|
Abstract |
A. Medi and W. Namgoong |
| University of Southern California, USA |
Session 7 |
High Speed Data Converters [Suzaku III] |
| Chairpersons |
M. Ito, Renesas Technology Corp.
K. Gulati, BitWave Semiconductor |
13:40 |
7-1 |
A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD
Converter in 0.13μm CMOS |
|
Abstract |
S.M. Louwsma, E.J.M. van Tuijl, M. Vertregt* and
B. Nauta |
| University of Twente and *NXP Semiconductors, The
Netherlands |
14:05 |
7-2 |
A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm
CMOS |
|
Abstract |
K. Deguchi, N. Suwa, M. Ito, T. Kumamoto and
T. Miki |
| Renesas Technology Corporation, Japan |
14:30 |
7-3 |
A 7b 1.1GS/s Reconfigurable Time-Interleaved
ADC in 90nm CMOS |
|
Abstract |
C.-C. Hsu*, C.-C. Huang*, Y.-H. Lin*, C.-C. Lee*,
Z. Soe**, T. Aytur** and R.-H. Yan** |
| *Realtek, Taiwan and **Realtek, USA |
14:55 |
7-4 |
A 12-GS/s Phase-Calibrated CMOS Digital-to-
Analog Converter |
|
Abstract |
J. Savoj, A. Abbasfar, A. Amirkhany*, M. Jeeradit and
B.W. Garlepp |
| Rambus, Inc. and *Stanford University, USA |
Session 8 |
Fuse Memories and SRAM Design Challenges
[Suzaku I] |
| Chairpersons |
K. Kajigaya, Elpida Memory, Inc.
S. Natarajan, Emerging Memory Technologies Inc. |
15:35 |
8-1 |
A Compact eFUSE Programmable Array Memory
for SOI CMOS |
|
Abstract |
J. Safran, A. Leslie, G. Fredeman, C. Kothandaraman,
A. Cestero, X. Chen, R. Rajeevakumar, D.-K. Kim,
Y.Z. Li, D. Moy, N. Robson, T. Kirihata and S. Iyer |
| IBM Microelectronics Division, USA |
16:00 |
8-2 |
A 512x8 Electrical Fuse Memory with 15μm2 Cells
Using 8-sq Asymmetric Fuse and Core Devices in
90nm CMOS |
|
Abstract |
S. Chung, J.-T. Huang, P. Chen and F.-L. Hsueh |
| Taiwan Semiconductor Manufacturing Corp., Ltd.,
Taiwan |
16:25 |
8-3 |
Effect of Power Supply Noise on SRAM Dynamic
Stability |
|
Abstract |
M. Khellah, D. Khalil*, D. Somasekhar, Y. Ismail*,
T. Karnik and V. De |
| Intel and *Northwestern University, USA |
16:50 |
8-4 |
A Sub-600mV, Fluctuation Tolerant 65nm CMOS
SRAM Array with Dynamic Cell Biasing |
|
Abstract |
A. Bhavnagarwala, S. Kosonocky, Y. Chan*,
K. Stawiasz, U. Srinivasan*, S. Kowalczyk and
M. Ziegler |
| IBM T.J. Watson Research Center and *IBM Systems
and Technology Group, USA |
17:15 |
8-5 |
Investigation of Increased Multi-Bit Failure Rate
Due to Neutron Induced SEU in Advanced
Embedded SRAMs |
|
Abstract |
G. Georgakos, P. Huber, M. Ostermayr, E. Amirante
and F. Ruckerbaur |
| Infineon Technologies AG, Germany |
Session 9 |
Low Power Wireless Communication [Suzaku II] |
| Chairpersons |
K. Agawa, Toshiba Corp.
M. Huang, Freescale Semiconductor Inc. |
15:35 |
9-1 |
A 2.4GHz ISM-Band Digital CMOS Wireless
Transceiver with an Intra-Symbol Adaptively
Intermittent Rx |
|
Abstract |
H. Ishizaki, K. Nose and M. Mizuno |
| NEC Corporation, Japan |
16:00 |
9-2 |
A CMOS UWB-IR Receiver Analog Front End
with Intermittent Operation |
|
Abstract |
T. Terada*,**, R. Fujiwara*,**, G. Ono*,**,
T. Norimatsu*,**, T. Nakagawa*,**,
K. Mizugaki*,**, M. Miyazaki*,**, K. Suzuki*,
K. Yano*, A. Maeki**, Y. Ogata**,
S. Kobayashi**,***, N. Koshizuka**,*** and
K. Sakamura**,*** |
| *Hitachi Ltd., **YRP Ubiquitous Networking
Laboratory and ***The University of Tokyo, Japan |
16:25 |
9-3 |
An Injection-Locked 5.2 GHz SoC Transceiver with
On-Chip Antenna for Self-Powered RFID and
Medical Sensor Applications |
|
Abstract |
P.H.R. Popplewell, V. Karam, A. Shamim, J. Rogers
and C. Plett |
| Carleton University, Canada |
16:50 |
9-4 |
1-cc Computer: Cross-Layer Integration with 3.4-
nW/bps Link and 22-cm Locationing |
|
Abstract |
G. Ono*,**, T. Nakagawa*,**, R. Fujiwara*,**,
T. Norimatsu*,**, T. Terada*,**, M. Miyazaki*,**,
K. Suzuki*,**, K. Yano*,**, Y. Ogata**, A. Maeki**,
S. Kobayashi**,***, N. Koshizuka**,*** and
K. Sakamura**,*** |
| *Hitachi, Ltd., **YRP Ubiquitous Networking
Laboratory and ***University of Tokyo, Japan |
17:15 |
9-5 |
AC Power Supply Circuits for Energy Harvesting |
|
Abstract |
J. Wenck*, R. Amirtharajah*, J. Collier** and
J. Siebert*** |
| *University of California, **Boston Scientific and
***Intel, USA |
Session 10 |
Analog Techniques [Suzaku III] |
| Chairpersons |
M. Ugajin, NTT
J. Gealow, Analog Devices, Inc. |
15:35 |
10-1 |
A Trimming-Free CMOS Bandgap-Reference
Circuit with Sub-1-V-Supply Voltage Operation |
|
Abstract |
Y. Okuda, T. Tsukamoto, M. Hiraki, M. Horiguchi and
T. Ito |
| Renesas Technology Corp., Japan |
16:00 |
10-2 |
A Very Wideband Fully Balanced Active RC
Polyphase Filter Based on CMOS Inverters in
0.18μm CMOS Technology |
|
Abstract |
K. Komoriyama, E. Yoshida, M. Yashiki and
H. Tanimoto |
| Kitami Institute of Technology, Japan |
16:25 |
10-3 |
A 5 kV HBM Transformer-Based ESD Protected 5-
6 GHz LNA |
|
Abstract |
J. Borremans*,**, S. Thijs**, P. Wambacq*,**,
D. Linten**, Y. Rolain* and M. Kuijk* |
| *Vrije Universiteit Brussel and **IMEC, Belgium |
16:50 |
10-4 |
An Integrated 1.2V-to-6V CMOS Charge-Pump for
Electret Earphone |
|
Abstract |
C.-Y. Tseng, S.-C. Chen, T.K. Shia* and P.-C. Huang |
| National Tsing Hua University and *ITRI, Taiwan |
17:15 |
10-5 |
Dual Threshold Preamplifier and Multi-Channel
DSP for Human Factored Digital Hearing Aid Chip |
|
Abstract |
S. Kim, S.J. Lee, N. Cho, S.-J. Song and H.-J. Yoo |
| KAIST, Korea |
Rump Sessions
|
Organizers |
K. Kobayashi, Kyoto Univ.
K. Yang, UCLA |
| R-1 |
Special Evening Talks: “Analog Scaling and SoC Integration”
[Suzaku I, II] |
Organizers |
A. Matsuzawa, Tokyo Institute of Technology
B. Nauta, University of Twente
|
1) What Should We Develop for Future RF Applications?
T. Ohguro, Toshiba
Recently, the telecommunication system has become complicated as
Multi-band and multi-system have been popular. And MOSFETs
with high RF performance has been required for mm-wave
application. In this session, we will discuss what technology and
elements we should develop for future RF application. Device
engineer has some questions. Advanced MOSFET with extremely
higher fT is the first priority? Or are high Q Inductor, high-density
capacitor or RF MEMS such as switch, variable capacitor, filter and
resonator more important?
2) Nanometer CMOS Trends: From Device Properties to Circuit
& System Performance
M. Vertregt, NXP Semiconducters
Implications of nanometer CMOS technology scaling (90nm, 65nm,
45nm and an outlook to 32nm) for the MOS device properties
relevant to circuit design will be explored. The demand is for high
speed and/or high dynamic range circuits, without compromising
power consumption. The possibilities to fulfill this demand in
combination with the inevitable increase of local and global
variabillity will be discussed.
3) SiP Versus SoC: RF System Partition for Cost and
Performance
A. Maxim, Silicon Laboratories
Partitioning the signal path of a radio receiver is crucial to the
overall system cost and performance. Two major integration
approaches have emerged: single-chip System-on-Chip (SoC) in
which both the sensitive RF front-end and the noisy digital back-end
are realized on the same die and multi-chip System-in-Package (SiP)
where the analog frond-end and the digital core are realized on
separate dies that are co-located in the same package. Design
challenges and circuit/system solutions are presented for both SoC
and SiP receivers. The different integration approaches including
single-chip RF-to-digital SoC, SiP assembly of a stand-alone tuner
and a demodulator-on-host, or between a tuner-demodulator and a
separate back-end MPEG host processor are investigated for the case
of satellite TV applications.
4) Challenges of Circuit Engineers to Analog Scaling
M. Hotta, Musashi Institute of Technology
K. Suyama, Epoch Microelectronics
In the case of mixed-signal system LSIs which integrate such analog
functions as ADCs, DACs and RF circuits, we are not allowed to
neglect the miniaturization and power reduction of analog portion
while CMOS technology scaling is progressed. Trends in
miniaturization and power reduction of analog functions will be
introduced and some challenges to overcome problems in use of
finer technologies will be discussed. |
R-2 |
CMOS Scaling: Where Will Economics Set the “End of the
Line”? [Suzaku III] |
Organizers |
K. Shepard, Columbia University
M. Hirata, NEC Electornics
|
Moderator |
S. Tam, Intel Corp.
|
Speakers |
I. Kawasaki, Renesas
Y.-C. Sun, TSMC
C. Kim, Samsung
S. Rusu, Intel
M. Polcari, Sematech
B. Rozich, IBM
|
| CMOS scaling is no longer making devices better or faster for digital
applications. Because of this, continued scaling is being driven
largely by the fact that scaling is still reducing the cost of a
transistor. Unfortunately, this a trend that cannot continue forever, as
tooling and fabrication challenges multiply for deeply-scaled CMOS
nodes. Where will economics set the “end of the line”? What players
or markets will determine this “end of line” scaling node? Will
FinFETs, double-gate structures (and other alternatives to
conventional CMOS devices) ever make sense from an economic
perspective? |
Session 11 |
Plenary Session II [Shunju I, II] |
| Chairpersons |
K. Yano, Hitachi, Ltd.
K. Nakamura, Analog Devices, Inc. |
8:30 |
11-1 |
High Performance Processor Development for
Consumer Electronics |
|
Invited |
J. Brown, IBM |
9:15 |
11-2 |
Ambient Electronics with Organic Transistors |
|
Invited |
T. Someya, University of Tokyo |
Session 12 |
Techniques for Signal and Power Integrity
[Shunju I] |
| Chairpersons |
M. Mizuno, NEC Corp.
A. Bhavnagarwala, IBM TJ Watson Research Center |
10:30 |
12-1 |
Silicon Odometer: An On-Chip Reliability Monitor
for Measuring Frequency Degradation of Digital
Circuits |
|
Abstract |
T.-H. Kim, R. Persaud and C.H. Kim |
| University of Minnesota, USA |
10:55 |
12-2 |
An On-Chip Noise Canceller with High Voltage
Supply Lines for Nanosecond-Range Power Supply
Noise |
|
Abstract |
Y. Nakamura, M. Takamiya and T. Sakurai |
| University of Tokyo, Japan |
11:20 |
12-3 |
A Switched Decoupling Capacitor Circuit for On-
Chip Supply Resonance Damping |
|
Abstract |
J. Gu, H. Eom and C.H. Kim |
| University of Minnesota, USA |
11:45 |
12-4 |
A 1.92μs-Wake-Up Time Thick-Gate-Oxide Power
Switch Technique for Ultra Low-Power Single-
Chip Mobile Processors |
|
Abstract |
K. Fukuoka, O. Ozawa, R. Mori, Y. Igarashi,
T. Sasaki, T. Kuraishi, Y. Yasu and K. Ishibashi |
| Renesas Technology Corp., Japan |
Session 13 |
High Speed Wireline [Shunju II] |
| Chairpersons |
H. Yamada, Oki Electric Industry Co., Ltd.
K. Yang, Univ. of California |
10:30 |
13-1 |
0.0234mm2/1mW DCO Based Clock/Data Recovery
for Gbit/s Applications |
|
Abstract |
K.-H. Chao, P.-Y. Wang and T.-H. Hsu |
| MediaTek Inc., Taiwan |
10:55 |
13-2 |
Precursor ISI Reduction in High-Speed I/O |
|
Abstract |
J. Ren*, H. Lee*, Q. Lin*, B. Leibowitz*,
E.-H. Chen**, D. Oh*, F. Lambrecht*,
V. Stojanovi´c*,***, C.-K.K. Yang** and J. Zerbe* |
| *Rambus, Inc, **University of California, Los Angeles
and ***Massachusetts Institute of Technology, USA |
11:20 |
13-3 |
A 8-Gbps Low-Latency Multi-Drop On-Chip
Transmission Line Interconnect with 1.2-mW Two-
Way Transceivers |
|
Abstract |
H. Ito, M. Kimura, K. Okada and K. Masu |
| Tokyo Institute of Technology, Japan |
11:45 |
13-4 |
1 Gbit/s Bidirectional Full-Wire Rate
Communication LSI for Residential Gateways |
|
Abstract |
Y. Nishida*, K. Kawai*, K. Koike*, K. Oyama**,
T. Hayashi** and H. Nouchi** |
| *NTT Cyber Solutions Laboratories and **NTT
Electronics Corporation, Japan |
Session 14 |
Sensors and Display [Shunju III] |
| Chairpersons |
K. Tani, Sanyo Electric Co., Ltd.
T. Blalock, Univ. of Virginia |
10:30 |
14-1 |
A 200-μV/e- CMOS Image Sensor with 100-ke- Full
Well Capacity |
|
Abstract |
S. Adachi*, W. Lee**, N. Akahane**, H. Oshikubo*,
K. Mizobuchi* and S. Sugawa** |
| *Texas Instruments Japan and **Tohoku University,
Japan |
10:55 |
14-2 |
A Single-Photon Avalanche Diode Imager for
Fluorescence Lifetime Applications |
|
Abstract |
D.E. Schwartz*, E. Charbon** and K.L. Shepard* |
| *Columbia University, USA and **EPFL, Switzerland |
11:20 |
14-3 |
A CMOS Readout Circuit for Silicon Resonant
Accelerometer with 32-ppb Bias Stability |
|
Abstract |
L. He, Y.P. Xu and M. Palaniapan |
| National University of Singapore, Singapore |
11:45 |
14-4 |
A Class AB Amplifier for LCD Driver |
|
Abstract |
R. Ito*, T. Itakura* and H. Minamizaki** |
| *Toshiba Corporation and **Semiconductor
Company, Toshiba Corporation, Japan |
Session 15 |
Low Power Circuit Techniques [Shunju I] |
| Chairpersons |
T. Shiota, Fujitsu Laboratories Ltd.
K. Shepard, Columbia Univ. |
13:30 |
15-1 |
Performance and Variability Optimization
Strategies in a Sub-200mV, 3.5pJ/inst, 11nW
Subthreshold Processor |
|
Abstract |
S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou,
M. Singhal, M. Minuth, J. Olson, L. Nazhandali,
T. Austin, D. Sylvester and D. Blaauw |
| University of Michigan, USA |
13:55 |
15-2 |
A 85mV 40nW Process-Tolerant Subthreshold 8x8
FIR Filter in 130nm Technology |
|
Abstract |
M.-E. Hwang, A. Raychowdhury, K. Kim and K. Roy |
| Purdue University, USA |
14:20 |
15-3 |
An Optimal Supply Voltage Determiner Circuit for
Minimum Energy Operations |
|
Abstract |
Y. Ikenaga, M. Nomura, Y. Nakazawa and
Y. Hagihara |
| NEC Corporation, Japan |
14:45 |
15-4 |
Skew-Tolerant Global Synchronization Based on
Periodically All-in-Phase Clocking for Multi-Core
SOC Platforms |
|
Abstract |
A. Shibayama, K. Nose, S. Torii, M. Mizuno and M.
Edahiro |
| NEC Corporation, Japan |
Session 16 |
Clock Generators and Time-to-Digital
Converters [Shunju II] |
| Chairpersons |
K. Tani, Sanyo Electric Co., Ltd.
B. Nauta, Univ. of Twente |
13:30 |
16-1 |
Timing Orthogonal Capacitance Multiplication
Technique for PLL |
|
Abstract |
P.-Y. Wang, S.-P. Chen and P. Chen |
| MediaTek Inc., Taiwan |
13:55 |
16-2 |
A 0.5-V 1.9-GHz Low-Power Phase-Locked Loop in
0.18-μm CMOS |
|
Abstract |
H.-H. Hsieh, C.-T. Lu and L.-H. Lu |
| National Taiwan University, Taiwan |
14:20 |
16-3 |
A Low Jitter 1.6 GHz Multiplying DLL Utilizing a
Scrambling Time-to-Digital Converter and Digital
Correlation |
|
Abstract |
B.M. Helal, M.Z. Straayer, G.-Y. Wei* and
M.H. Perrott |
| Massachusetts Institute of Technology and *Harvard
University, USA |
14:45 |
16-4 |
A 9b, 1.25ps Resolution Coarse-Fine Time-to-
Digital Converter in 90nm CMOS that Amplifies a
Time Residue |
|
Abstract |
M. Lee and A.A. Abidi |
| University of California, USA |
Session 17 |
MM-Wave Building Blocks [Shunju III] |
| Chairpersons |
H. Ishikuro, Keio Univ.
F. Dai, Auburn Univ. |
13:30 |
17-1 |
A 60-GHz CMOS Receiver with Frequency
Synthesizer |
|
Abstract |
T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana,
H. Hoshino, Y. Yoshihara, Y. Tsutsumi and
I. Seto |
| Toshiba Corporation, Japan |
13:55 |
17-2 |
A 75GHz PLL Front-End Integration in 65nm SOI
CMOS Technology |
|
Abstract |
D. Kim*, J. Kim*, J.-O. Plouchart**, C. Cho*,
D. Lim***, W. Li**** and R. Trzcinski** |
| *IBM Semiconductor Research and Development
Center, **IBM T. J. Watson Research Center,
***Massachusetts Institute of Technology and
****Yale University, USA |
14:20 |
17-3 |
76GHz CMOS Voltage-Controlled Oscillator with
7% Frequency Tuning Range |
|
Abstract |
K. Ishibashi, M. Motoyoshi, N. Kobayashi and
M. Fujishima |
| The University of Tokyo, Japan |
14:45 |
17-4 |
A 63-GHz Voltage-Controlled Oscillator in 0.18-μm
CMOS |
|
Abstract |
H.-H. Hsieh and L.-H. Lu |
| National Taiwan University, Taiwan |
Session 18 |
Dynamic & Nonvolatile Memories [Shunju I] |
| Chairpersons |
C. Kim, Samsung Electronics Co., Ltd.
H. Pon, Intel Corp. |
15:25 |
18-1 |
A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an
Address Queuing Scheme and Bang-Bang Jitter
Reduced DLL Scheme |
|
Abstract |
Y.K. Kim, B.H. Jeong, Y.J. Jeon, N.W. Heo,
S.B. Chang, H.G. Jung, D.Y. Kim, H.J. Chung,
C.S. Kim, S.B. Ko, K.H. Kyung, J.H. Yoo and
S.I. Cho |
| Samsung Electronics Company, Korea |
15:50 |
18-2 |
Processor-Based Built-in Self-Optimizer for 90nm
Diode-Switch PRAM |
|
Abstract |
K. Sohn*, H. Kim*, J. Yoo*, J.-H. Woo*, S.-J. Lee*,
W.-Y. Cho**, B.-T. Lim**, B.-G. Choi**,
C.-S. Kim**, C.-K. Kwak**, C.-H. Kim** and
H.-J. Yoo* |
| *KAIST and **Samsung Electronics, Korea |
16:15 |
18-3 |
Time Discrete Voltage Sensing and Iterative
Programming Control for a 4F2 Multilevel CBRAM |
|
Abstract |
P. Schrögmeier*, M. Angerbauer*, S. Dietrich*,
M. Ivanov*, H. Hönigschmid*, C. Liaw*,
M. Markert*, R. Symanczyk*, L. Altimime*,
S. Bournat** and G. Müller* |
| *Qimonda AG, Germany and **Altis Semiconductor,
France |
16:40 |
18-4 |
A Zeroing Cell-to-Cell Interference Page
Architecture with Temporary LSB Storing
Program Scheme for Sub-40nm MLC NAND Flash
Memories and Beyond |
|
Abstract |
K.-T. Park, M. Kang, D. Kim, S. Hwang, Y.-T. Lee,
C. Kim and K. Kim |
| Samsung Electronics Co., Ltd., Korea |
17:05 |
18-5 |
A 70nm 16Gb 16-Level-Cell NAND Flash Memory |
|
Abstract |
N. Shibata, H. Maejima, K. Isobe, K. Iwasa,
M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma,
S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa,
H. Tabata, A. Inoue, T. Takahashi, T. Shano,
Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi,
K. Kanazawa, K. Imamiya and H. Nakai |
| Toshiba Corporation Semiconductor Company, Japan |
| (Dinner 18:00-20:00 [Suzaku]) |
Session 19 |
Nyquist Data Converters [Shunju II] |
| Chairpersons |
M. Song, Dongguk Univ.
T. Kwan, Broadcom Corp. |
15:25 |
19-1 |
A 2.5mW 80dB DR 36dB SNDR 22MS/s
Logarithmic Pipeline ADC |
|
Abstract |
J. Lee, S. Park, J. Kang, J.-S. Seo, J. Anders and
M. Flynn |
| University of Michigan, USA |
15:50 |
19-2 |
A 14b Low-power Pipeline A/D Converter Using a
Pre-charging Technique |
|
Abstract |
K. Honda, Z. Liu, M. Furuta and S. Kawahito |
| Shizuoka University, Japan |
16:15 |
19-3 |
A 90nm CMOS 0.28mm2 1V 12b 40MS/s ADC with
0.39pJ/Conversion-Step |
|
Abstract |
K.-J. Lee, E.-S. Shin, H.-S. Yang, J.-H. Kim, P.-U. Ko,
I.-R. Kim, S.-H. Lee, K.-H. Moon and J.-W. Kim |
| Samsung Electronics Co., Ltd, Korea |
16:40 |
19-4 |
A 150MS/s 14-bit Segmented DEM DAC with
Greater than 83dB of SFDR Across the Nyquist
Band |
|
Abstract |
K.L. Chan, J. Zhu and I. Galton |
| University of California, San Diego, USA |
17:05 |
19-5 |
A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS |
|
Abstract |
J. Shen and P. Kinget |
| Columbia University, USA |
| (Dinner 18:00-20:00 [Suzaku]) |
Session 20 |
Tuners / Receiver and RF Test [Shunju III] |
| Chairpersons |
M. Ugajin, NTT
M. Huang, Freescale Semiconductor Inc. |
15:25 |
20-1 |
0.13μ CMOS Hybrid TV Tuner Using a Calibrated
Image and Harmonic Rejection Mixer |
|
Abstract |
A. Maxim, R. Johns and S. Dupue |
| Silicon Inc., USA |
15:50 |
20-2 |
A Fully Integrated Low-IF Image Reject Receiver
for T-DMB and DAB Applications |
|
Abstract |
K. Lim, S. Min, M.-W. Hwang, S. Lee, T.-J. Kim,
S. Beck, S. Ock, J.-C. Lee, H. Jung, S. Hong, M. Ahn,
H. Song, S. Shin, S. Lee, S. Yoo, J. Kim and S. Han |
| Future Communication IC (FCI) Inc., Korea |
16:15 |
20-3 |
Zero-Second-IF SiGe BiCMOS Satellite Radio
Tuner Using a Dual RF/IF AGC Loop |
|
Abstract |
A. Maxim, M. Gheorge and C. Turinici |
| Maxim Inc., USA |
16:40 |
20-4 |
A 0.016mm2, 2.4GHz RF Signal Quality
Measurement Macro for RF Test and Diagnosis |
|
Abstract |
K. Nose and M. Mizuno |
| NEC Corporation, Japan |
| (Dinner 18:00-20:00 [Suzaku]) |
Session 21 |
Processors for Mobile Applications [Shunju I] |
| Chairpersons |
H. Kabuo, Matsushita Electric Industrial Co., Ltd.
B. Nikolic, Univ. of California |
8:30 |
21-1 |
Homogenous Dual-Processor Core with Shared L1
Cache for Mobile Multimedia SoC |
|
Abstract |
M. Nakajima, T. Yamamoto, M. Yamasaki, K. Kaneko
and T. Hosoki |
| Matsushita Electric Industrial Co., Ltd, Japan |
8:55 |
21-2 |
An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2
Stream Processor Core for Mobile Graphics and
Video Applications |
|
Abstract |
Y.-M. Tsao, C.-H. Chang, Y.-C. Lin, S.-Y. Chien and
L.-G. Chen |
| National Taiwan University, Taiwan |
9:20 |
21-3 |
A 152mW Mobile Multimedia SoC with Fully
Programmable 3D Graphics and
MPEG4/H.264/JPEG |
|
Abstract |
J.-H. Woo*, J.-H. Sohn*, H. Kim*, J. Jeong**,
E. Jeong**, S.J. Lee** and H.-J. Yoo* |
| *KAIST and **Corelogic, Inc., Korea |
9:45 |
21-4 |
2.8 to 67.2mW Low-Power and Power-Aware H.264
Encoder for Mobile Applications |
|
Abstract |
T.-C. Chen, Y.-H. Chen, C.-Y. Tsai, S.-F. Tsai,
S.-Y. Chien and L.-G. Chen |
| National Taiwan University, Taiwan |
10:10 |
21-5 |
A 65-nm Mobile Multimedia Applications
Processor with an Adaptive Power Management
Scheme to Compensate for Variations |
|
Abstract |
H. Mair, A. Wang, G. Gammie, D. Scott, P. Royannez,
S. Gururajarao, M. Chau, R. Lagerquist, L. Ho,
M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan,
J. Song, B. Carlson and U. Ko |
| Texas Instruments Inc., USA |
Session 22 |
Advanced DLL and PLLs [Shunju II] |
| Chairpersons |
M. Nagata, Kobe Univ.
S. Tam, Intel Corp. |
8:30 |
22-1 |
Multiphase-Output Level Shift System used in
Multiphase PLL for Low Power Application |
|
Abstract |
A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie
and S. Dosho |
| Matsushita Electric Industrial Co., Ltd, Japan |
8:55 |
22-2 |
A Fully Integrated 36MHz to 230MHz Multiplying
DLL with Adaptive Current Tuning |
|
Abstract |
K.-J. Hsiao and T.-C. Lee |
| National Taiwan University, Taiwan |
9:20 |
22-3 |
A PVT Tolerant PLL with On-Chip Loop-
Transfer-Function Calibration Circuit |
|
Abstract |
M. Kondou* and T. Mori** |
| *Fujitsu Laboratories Ltd and **Fujitsu Limited,
Japan |
9:45 |
22-4 |
A Dual PFD Phase Rotating Multi-Phase PLL for
5Gbps PCI Express Gen2 Multi-Lane Serial Link
Receiver in 0.13um CMOS |
|
Abstract |
S. Kim, D. Lee, Y.-S. Park*, Y. Moon** and D. Shim |
| Silicon Image Inc., *GCT Semiconductor Inc., USA
and **Samsung Electronics, Korea |
Session 23 |
Oversampled Data Converters [Shunju III] |
| Chairpersons |
M. Ito, Renesas Technology Corp.
L. Breems, NXP Semiconductors |
8:30 |
23-1 |
A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-
Time Cascaded ΣΔ Modulator |
|
Abstract |
S.D. Kulchycki, R. Trofin, K. Vleugels and
B.A. Wooley |
| Stanford University, USA |
8:55 |
23-2 |
A Low Power Sigma-Delta Modulator Using Class-
C Inverter |
|
Abstract |
Y. Chae and G. Han |
| Yonsei University, Korea |
9:20 |
23-3 |
A Split 2-0 MASH with Dual Digital Error
Correction |
|
Abstract |
Z. Zhang*, J. Steensgaard**, G.C. Temes* and
J.-Y. Wu*** |
| *Oregon State University, **Esion LLC and
***National Semiconductor, USA |
9:45 |
23-4 |
A High-Resolution Low-Power Oversampling ADC
with Extended-Range for Bio- Sensor Arrays |
|
Abstract |
A. Agah*,**, K. Vleugels***, P.B. Griffin*,
M. Ronaghi**, J.D. Plummer* and B.A. Wooley* |
| *Stanford University, **Stanford Genome Technology
Center and ***H-Stream Wireless, USA |
10:10 |
23-5 |
A 10-Bit 20MHz 38mW 950MHz CT ΣΔ ADC with
a 5-Bit Noise-Shaping VCO-Based Quantizer and
DEM Circuit in 0.13u CMOS |
|
Abstract |
M.Z. Straayer and M.H. Perrott |
| Massachusetts Institute of Technology, USA |
Session 24 |
Embedded SRAMs [Shunju I] |
| Chairpersons |
T. Sekiguchi, Hitachi Ltd.
V. De, Intel Corp. |
10:50 |
24-1 |
6.6+ GHz Low Vmin, Read and Half Select
Disturb-Free 1.2 Mb SRAM |
|
Abstract |
R. Joshi, R. Houle, K. Batson, D. Rodko, P. Patel,
W. Huott, R. Franch, Y. Chan, D. Plass, S. Wilson and
P. Wang |
| IBM, USA |
11:15 |
24-2 |
A 5.3GHz 8T-SRAM with Operation Down to
0.41V in 65nm CMOS |
|
Abstract |
L. Chang, Y. Nakamura*, R.K. Montoye, J. Sawada**,
A.K. Martin**, K. Kinoshita*, F.H. Gebara**,
K.B. Agarwal**, D.J. Acharyya, W. Haensch,
K. Hosokawa* and D. Jamsek** |
| IBM T. J. Watson Research Center, USA, *IBM TCS,
Japan and **IBM Austin Research Lab, USA |
11:40 |
24-3 |
A 45nm 2port 8T-SRAM Using Hierarchical
Replica Bitline Technique with Immunity from
Simultaneous R/W Access Issues |
|
Abstract |
S. Ishikura*, M. Kurumada*, T. Terano*,
Y. Yamagami*, N. Kotani*, K. Satomi*, K. Nii**,
M. Yabuuchi**, Y. Tsukamoto**, S. Ohbayashi**,
T. Oashi**, H. Makino**, H. Shinohara** and
H. Akamatsu* |
| *Matsushita Electric Industrial Co., Ltd. and
**Renesas Technology Corporation, Japan |
12:05 |
24-4 |
An Area-Conscious Low-Voltage-Oriented 8TSRAM
Design Under DVS Environment |
|
Abstract |
Y. Morita*, H. Fujiwara*, H. Noguchi*, Y. Iguchi*,
K. Nii*,**, H. Kawaguchi* and M. Yoshimoto* |
| *Kobe University and **Renesas Technology
Corporation, Japan |
Session 25 |
Frequency Synthesizer [Shunju II] |
| Chairpersons |
H. Ishikuro, Keio Univ.
C.M. Hung, Texas Instruments, Inc. |
10:50 |
25-1 |
Fast-locking Hybrid PLL Synthesizer Combining
Integer & Fractional Divisions |
|
Abstract |
K. Woo, Y. Liu and D. Ham |
| Harvard University, USA |
11:15 |
25-2 |
A CMOS ΔΣ Fractional-N Frequency Synthesizer
with Quantization Noise Pushing Technique |
|
Abstract |
Y.-C. Yang and S.-S. Lu |
| National Taiwan University, Taiwan |
11:40 |
25-3 |
A 21-GHz Fractional-N Synthesizer in 130-nm
CMOS |
|
Abstract |
Y. Ding and K.K. O |
| University of Florida, USA |
12:05 |
25-4 |
A Wide Locking Range and Low Power V-band
Frequency Divider in 90nm CMOS |
|
Abstract |
Q. Gu*, Z. Xu*,** and M.-C.F. Chang* |
| *University of California, Los Angeles and **SST
Communications, USA |
Session 26 |
High Bit Rate Wireline [Shunju III] |
| Chairpersons |
H. Yamada, Oki Electric Industry Co., Ltd.
A. Maxim, Silicon Laboratories, Inc. |
10:50 |
26-1 |
A Scalable 5-15Gbps, 14-75mW Low Power I/O
Transceiver in 65nm CMOS |
| Abstract |
G. Balamurugan, J. Kennedy, G. Banerjee, J.E. Jaussi,
M. Mansuri, F. O’Mahony, B. Casper and R. Mooney |
| Intel Corporation, USA |
11:15 |
26-2 |
An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap
DFE Receiver in 65nm CMOS |
| Abstract |
A. Rylyakov |
| IBM T.J. Watson Research Center, USA |
11:40 |
26-3 |
A Jitter-Tolerance-Enhanced CDR Using a GDCOBased
Phase Detector |
| Abstract |
C.-F. Liang, S.-C. Hwu and S.-I. Liu |
| National Taiwan University, Taiwan |
12:05 |
26-4 |
18Gb/s Optical IO: VCSEL Driver and TIA in
90nm CMOS |
| Abstract |
A. Kern*, A. Chandrankasan* and I. Young** |
| *Massachusetts Institute of Technology and **Intel
Corporation, USA |
|
