3D LSI integration and packaging have been discussed for decades. Is TSV just the latest buzz-word or will it become a mainstream process? The panel will discuss which applications (memory, processor, memory+processor, imager, mixed-signal, FPGA or others) are driving the development of TSV and what types of applications could benefit from TSV in the future. The panel will debate how these applications get an advantage in the marketplace from TSV, which they cannot get from other 3D LSI integration or packaging technologies in manufacturing today.

We have assembled a distinguished panel of experts who will discuss and debate these questions and more as they explore the prospects of TSV for 3D LSI and packaging.

- Does TSV offer design, test, performance, yield, thermal / power or cost advantages over existing 3D technologies?
- What are main challenges and limitations for the acceptance in mainstream applications?
- Who will offer TSV as a design solution; IDM’s, Foundries and/or OSAT’s?

When scaling down CMOS technology towards the 16nm node, the semiconductor community is facing serious challenges. At the 32nm node continued scaling for high performance and low power CMOS technologies have been achieved with the introduction of immersion lithography combined with double patterning and resolution enhancement techniques, multiple highly optimized and additive strain techniques, and the biggest innovation since 40 years of CMOS scaling, that certainly is high-k gate dielectric and metal gate. Today, the trends in research and development indicate that at the 22nm node existing solutions will be finally further scaled and optimized, and some new still evolutionary features like Si:C material for source/drain introduced to improve device performance and scaling.

For 16nm it is expected that controlling power and variability and simultaneously improving circuit performance will become the biggest challenge. Since the further scaling of the high-k / metal gate stack imposes fundamental problems as well as strain techniques are approaching their limit, the use of new device architectures such as ultra thin body SOI, Multi-Gate FET for short channel effect control or even alternative high mobility channel materials as performance boosters are possibly required. In this regard, the 16nm node may be the revolutionary and for a long time predicted departure from the “conventional” CMOS technology scaling. As a consequence, the technology options will have an increasing impact on circuit design and layout techniques.

This panel discussion will address the key technology challenges as well as enabling options for scaling down CMOS devices towards 16nm node. Which 16nm transistor structures are the most viable for logic and SRAM application? What determines the transistor architecture – density, performance, power, variability, complexity, manufacturability? What are the emerging challenges with device parasitics? What are the potential solutions in Lithography and how do they impact the transistor architecture? Finally, how do the different technology solutions (including new device architectures, immersion and EU lithography, double patterning and resolution enhancement techniques) impact circuit design and chip layout?

The distinguished panelist will also give an outlook on the viability of the technology solutions being discussed to extend Moore’s Law beyond the 16nm node towards the end of the roadmap.